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专利名称：Pipelined processor which reduces branch
instruction interlocks by compensating formisaligned branch instructions
发明人：Masato Suzuki申请号：US08/562069申请日：19951122公开号：US05729727A公开日：19980317
摘要：A processor for executing branch instructions each including a branchprocedure and another procedure includes the following units. A prefetch unit
prefetches instructions from memory and updates a prefetch address which is held in theprefetch unit. A control unit controls an execution of the branch procedure and anexecution of the other procedure, which follows the execution of the branch procedure.The branch procedure is to write the prefetch address held in the prefetch unit intobranch target address. The prefetch unit sequentially prefetches instructions which startat the branch target address when the other procedure is in execution.
申请人：MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
代理机构：Price, Gess & Ubell
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