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专利名称：Memory system having an encoding
processing circuit for redundant encodingprocess
发明人：Masaya Tarui,Tatsunori Kanai,Yutaka Yamada申请号：US13157396申请日：20110610公开号：US09105358B2公开日：20150811
专利附图：
摘要：In one embodiment, a memory system for writing redundant data output by anencoding processing circuit, comprises a memory, a encoding processing circuit, and a
decoding circuit. The memory is electrically rewritable by using memory cells. Thememory cells are capable of having two different resistance values corresponding tological values of 1 or 0 respectively. The redundant data is read from and apredetermined logical value is written to the memory by flowing current in a samedirection. The encoding processing circuit performs redundant encoding processing ontarget data and outputs redundant data. A number of bits having the predeterminedlogical value exceeds a number of bits having the logical value other than the
predetermined logical value, for writing the redundant data to the memory. A decodingcircuit reads data from the memory, and performs a decoding process on the data.
申请人：Masaya Tarui,Tatsunori Kanai,Yutaka Yamada
地址：Yokohama JP,Yokohama JP,Kawasaki JP
国籍：JP,JP,JP
代理机构：Amin, Turocy & Watson, LLP
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