MC100EP446FAG资料

MC10EP446, MC100EP4463.3 V/5 V 8-Bit

CMOS/ECL/TTL Data InputParallel/Serial Converter

Description

The MC10/100EP446 is an integrated 8−bit parallel to serial dataconverter. The device is designed with unique circuit topology tooperate for NRZ data rates up to 3.2 Gb/s. The conversion sequencefrom parallel data into a serial data stream is from bit D0 to D7. Theparallel input pins D0−D7 are configurable to be threshold controlled byCMOS, ECL, or TTL level signals. The serial data rate output can beselected at internal clock data rate or twice the internal clock data rateusing the CKSEL pin.

Control pins are provided to reset (SYNC) and disable internal clockcircuitry (CKEN). In either CKSEL modes, the internal flip−flops aretriggered on the rising edge for CLK and the multiplexers are switchedon the falling edge of CLK, therefore, all associated specificationlimits are referenced to the negative edge of the clock input.Additionally, VBB pin is provided for single−ended input condition.The 100 Series devices contain temperature compensation network.

Features

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MARKING DIAGRAMS*MCxxxEP446AWLYYWWGLQFP−32FA SUFFIXCASE 873A1••••••••••

3.2 Gb/s Typical Data Rate CapabilityDifferential Clock and Serial Outputs

VBB Output for Single-ended Input ApplicationsAsynchronous Data Reset (SYNC)PECL Mode Operating Range:

VCC = 3.0 V to 5.5 V with VEE = 0 V

NECL Mode Operating Range:

VCC = 0 V with VEE = −3.0 V to −5.5 V

Open Input Default StateSafety Clamp on Inputs

Parallel Interface Can Support PECL, TTL or CMOSPb−Free Packages are Available*

132QFN32MN SUFFIXCASE 488AMMCxxxEP446AWLYYWWGGxxx= 10 or 100A= Assembly LocationWL, L= Wafer LotYY, Y= YearWW, W= Work WeekG or G= Pb−Free Package(Note: Microdot may be in either location)*For additional marking information, refer to Application Note AND8002/D.ORDERING INFORMATION

See detailed ordering and shipping information in the packagedimensions section on page 18 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2007

February, 2007 − Rev. 9

1

Publication Order Number:

MC10EP446/D

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MC10EP446, MC100EP446

D0D1D2D3D4D5D6D7D2D5D0D1D3D4D618

24

VCCVCFVEFVEESYNCSYNCVBB2VCC

2526272829303132

1

23222120191817161514

VEEPCLKPCLKVCC

242322212019

VCCVCFVEFVEE

D717

161514131211109

2526272829303132

1

2

3

4

5

6

7

8

VEEPCLKPCLKVCCSOUTSOUTVCCVCC

MC10EP446MC100EP446

131211109

Exposed Pad (EP)

SOUTSYNCSOUTSYNCVCCVCC

VBB2VCC

2345678

CKENCKENCLKCLKCKENCKENCLKCLKWarning: All VCC and VEE pins must be externally connectedto Power Supply to guarantee proper operation.

CKSELVBB1VCCVEEFigure 1. LQFP−32 Pinout (Top View)Figure 2. QFN−32 Pinout (Top View)

Table 1. PIN DESCRIPTION

PIN

D0*−D7*SOUT, SOUTCLK*, CLK*PCLK, PCLKSYNC*, SYNC**CKSEL*CKEN*, CKEN*VCFVEFVBB1, VBB2VCCVEE

ECL, CMOS, or TTL Parallel Data InputECL Differential Serial Data OutputECL Differential Clock Input

ECL Differential Parallel Clock Output

ECL Conversion Synchronizing Differential Input (Reset)***ECL Clock Input Selector

ECL Clock Enable Differential InputECL, CMOS, or TTL Input SelectorECL Reference Mode ConnectionReference Voltage OutputPositive SupplyNegative Supply

FUNCTION

*Pins will default LOW when left open.**Pins will default HIGH when left open.

***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLKinitiates the conversion process synchronously on the next rising edge of CLK.

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MC10EP446, MC100EP446

Table 2. TRUTH TABLE

FunctionPinCKSELSOUT: PCLK = 8:1CLK: SOUT = 1:1CLKSOUTCKENSYNCSynchronously Disables Normal Parallel to SerialConversionAsynchronously Resets Internal Flip−Flops*HIGHSOUT: PCLK = 8:1CLK: SOUT = 1:2CLKSOUTSynchronously Enables Normal Parallel to Serial ConversionSynchronous EnableLOW*The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiatesthe conversion process synchronously on the next rising edge of CLK.

Table 3. INPUT VOLTAGE LEVEL SELECTION TABLE

Input FunctionECL ModeCMOS ModeTTL Mode*

Connect To VCF Pin

VEF PinNo Connect1.5 V $ 100 mV

Table 4. DATA INPUT OPERATING VOLTAGE TABLE

Power Supply(VCC,VEE)

PECLNECL

Data Inputs (D [0:7])

CMOSpN/A

TTLpN/A

PECLpN/A

NECLN/Ap

*For TTL Mode, if no external voltage can be provided, the referencevoltage can be provided by connecting the appropriate resistorbetween VCF and VEE pins.

Power Supply

3.3 V5.0 V

Resistor Value 10% (Tolerance)

1.5 kW500 W

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MC10EP446, MC100EP446

D0DCRQMUX2:1QDCRQD4DCRMUX2:1QMUX2:1QDCRQDCRQD2DCRD6DCRMUX2:1QMUX2:1QDCRQSOUTSOUTD1DCRD5DCRMUX2:1QMUX2:1QDCRQDCRQD3DCRD7DCR÷2÷2PCLKPCLK÷2CKENCKENCLKCLKCKSELSYNCVCCVEE

SYNC

VBBVCFVEFDCRQMUX2:1ControlLogicFigure 3. Logic Diagram

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MC10EP446, MC100EP446

Table 5. ATTRIBUTES

Characteristics

Internal Input Pulldown ResistorInternal Input Pullup ResistorESD Protection

Human Body Model

Machine Model

Charged Device Model

Pb PkgLevel 2−

Value75 kW37.5 kW> 2 kV> 100 V> 2 kV

Pb−Free PkgLevel 2Level 1

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

LQFP−32QFN−32

Flammability RatingTransistor Count

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test1.For additional information, see Application Note AND8003/D.

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

962 Devices

Table 6. MAXIMUM RATINGS

SymbolVCCVEEVIIoutIBBTATstgqJAqJCqJAqJCTsol

Parameter

PECL Mode Power SupplyNECL Mode Power SupplyPECL Mode Input VoltageNECL Mode Input VoltageOutput CurrentVBB Sink/Source

Operating Temperature RangeStorage Temperature Range

Thermal Resistance (Junction−to−Ambient)Thermal Resistance (Junction−to−Case)Thermal Resistance (Junction−to−Ambient)Thermal Resistance (Junction−to−Case)Wave Solder

PbPb−Free

0 lfpm500 lfpmStandard Board0 lfpm500 lfpm2S2P

<2 to 3 sec @ 248°C<2 to 3 sec @ 260°C

LQFP−32LQFP−32LQFP−32QFN−32QFN−32QFN−32

Condition 1VEE = 0 VVCC = 0 VVEE = 0 VVCC = 0 VContinuousSurge

VI ≤ VCCVI ≥ VEE

Condition 2

Rating6−66−650100± 0.5−40 to +85−65 to +150

805512 to 17312712265265

UnitVVVmAmA°C°C°C/W°C/W°C/W°C/W°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.

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MC10EP446, MC100EP446

Table 7. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)

−40°C

SymbolIEEVOHVOLVIH

Characteristic

Power Supply CurrentOutput HIGH Voltage (Note 3)Output LOW Voltage (Note 3)Input HIGH Voltage (Single−Ended)

CMOSPECLTTL

Input LOW Voltage (Single−Ended)

CMOSPECLTTL

Output Voltage Reference

Input HIGH Voltage Common Mode Range (Dif-ferential Configuration) (Note 4)Input HIGH CurrentInput LOW Current

(All Except SYNC, SYNC)SYNC, SYNC0.5−15001365017902.0

1840

800169080019903.31500.5

0.5−15001460018552.0

1905

800175580020553.31500.5

0.5−15001490019152.0

1965

800181580021153.31500.5

200020902000

330033003300

200021552000

330033003300

200022152000

330033003300

Min9021651365

Typ11022901490

Max14024151615

Min9022301430

25°CTyp11023551555

Max14024801680

Min9522901490

85°CTyp11524151615

Max14525401740

UnitmAmVmVmV

VIL

mV

VBBVIHCMRIIHIIL

mVVmAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

2.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.3.All loading with 50 W to VCC − 2.0 V.

4.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

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MC10EP446, MC100EP446

Table 8. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)

−40°C

SymbolIEEVOHVOLVIH

Characteristic

Power Supply CurrentOutput HIGH Voltage (Note 6)Output LOW Voltage (Note 6)Input HIGH Voltage (Single−Ended)

CMOSPECLTTL

Input LOW Voltage (Single−Ended)

CMOSPECLTTL

Output Voltage Reference

Input HIGH Voltage Common Mode Range (Dif-ferential Configuration) (Note 7)Input HIGH CurrentInput LOW Current

(All Except SYNC, SYNC)SYNC, SYNC0.5−15003065034902.0

3540

1500339080036905.01500.5

0.5−15003130035552.0

3605

1500345580037555.01500.5

0.5−15003190036152.0

3665

1500391580038155.01500.5

350037902000

500050005000

350038552000

500050005000

350039152000

500050005000

Min9038653065

Typ11039503190

Max14041153315

Min9039303130

25°CTyp11040553255

Max14041803380

Min9539903190

85°CTyp11541153315

Max14542403440

UnitmAmVmVmV

VIL

mV

VBBVIHCMRIIHIIL

mVVmAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

5.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.6.All loading with 50 W to VCC − 2.0 V.

7.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

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MC10EP446, MC100EP446

Table 9. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 8)

−40°C

SymbolIEEVOHVOLVIHVILVBBVIHCMR

Characteristic

Power Supply CurrentOutput HIGH Voltage (Note 9)Output LOW Voltage (Note 9)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Output Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 10)

Input HIGH Current

Input LOW Current

(All Except SYNC, SYNC)SYNC, SYNC0.5−150Min90−1135−1935−1210−1935−1510

−1460Typ110−1010−1810

Max140−885−1685−885−1610−13100.0

Min90−1070−1870−1145−1870−1445

−139525°CTyp110−945−1745

Max140−820−1620−820−1545−12450.0

Min95−1010−1810−1085−1810−1385

−133585°CTyp115−885−1685

Max145−760−1560−760−1485−11850.0

UnitmAmVmVmVmVmVV

VEE+2.0VEE+2.0VEE+2.0

IIHIIL

150

0.5−150

150

0.5−150

150mAmA

0.50.50.5

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

8.Input and output parameters vary 1:1 with VCC.9.All loading with 50 W to VCC − 2.0 V.

10.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

Table 10. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)

−40°C

SymbolIEEVOHVOLVIH

Characteristic

Power Supply Current

Output HIGH Voltage (Note 12)Output LOW Voltage (Note 12)Input HIGH Voltage (Single−Ended)

CMOSPECLTTLInput LOW Voltage (Single−Ended)

CMOSPECLTTLOutput Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 13)

Input HIGH CurrentInput LOW Current

0.5Min902155135520002075200001355017752.0

1875Typ11022801480

Max13024051605330033003300800167580019753.3

Min902155135520002075200001355017752.0

187525°CTyp11022801480

Max13024051605330033003300800167580019753.3

Min952155135520002075200001355017752.0

187585°CTyp11522801480

Max13524051605330033003300800167580019753.3

UnitmAmVmVmV

VIL

mV

VBBVIHCMR

mVV

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

11.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.12.All loading with 50 W to VCC − 2.0 V.

13.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

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MC10EP446, MC100EP446

Table 11. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)

−40°C

SymbolIEEVOHVOLVIH

Characteristic

Power Supply Current

Output HIGH Voltage (Note 15)Output LOW Voltage (Note 15)Input HIGH Voltage (Single−Ended)

CMOSPECLTTLInput LOW Voltage (Single−Ended)

CMOSPECLTTLOutput Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 16)

Input HIGH CurrentInput LOW Current

0.5Min903855305535003775200003055034752.0

3575Typ11039803180

Max130410533055000500050001500337580036755.0

Min903855305535003775200003055034752.0

357525°CTyp11039803180

Max130410533055000500050001500337580036755.0

Min953855305535003775200003055034752.0

357585°CTyp11539803180

Max135410533055000500050001500337580036755.0

UnitmAmVmVmV

VIL

mV

VBBVIHCMR

mVV

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

14.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.15.All loading with 50 W to VCC − 2.0 V.

16.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

Table 12. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 17)

−40°C

SymbolIEEVOHVOLVIHVILVBBVIHCMR

Characteristic

Power Supply Current

Output HIGH Voltage (Note 18)Output LOW Voltage (Note 18)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Output Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 19)

Input HIGH CurrentInput LOW Current

0.5Min90−1145−1945−1225−1945−1525

−1425Typ110−1020−1820

Max130−5−1695−880−1625−13250.0

Min90−1145−1945−1225−1945−1525

−142525°CTyp110−1020−1820

Max130−5−1695−880−1625−13250.0

Min95−1145−1945−1225−1945−1525

−142585°CTyp115−1020−1820

Max135−5−1695−880−1625−13250.0

UnitmAmVmVmVmVmVV

VEE+2.0VEE+2.0VEE+2.0

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

17.Input and output parameters vary 1:1 with VCC.18.All loading with 50 W to VCC − 2.0 V.

19.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

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MC10EP446, MC100EP446

Table 13. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)

−40°C

Symbolfmax

Characteristic

Maximum Frequency(Figure 15)

CKSEL HighCKSEL Low

tPLH,tPHL

Propagation Delay to Output DifferentialCKSEL = 0CLK TO SOUT,

CLK TO PCLKCKSEL = 1

tS

CLK TO SOUT,CLK TO PCLK

3.21.6650700775850

3.41.7750800875950

8509009751050

3.21.6700750825900−40020070−550075150200145

0.2

150

SOUT

50

800100

< 11200150

15070

0.2800120

< 11200170

15090

3.41.78008509251000−45014040−60045

90095010251100

3.21.6725775875950−45020070−600075150200145

0.2800140

< 11200190

3.41.785090010001075−50014040−65045

ps

975102511251200

Min

Typ

Max

Min

25°CTyp

Max

Min

85°CTyp

Max

Unit

GHz

psps

Setup TimeD to CLK+ (Figure 4)−375−425SYNC− to CLK− (Figure 5)200140CKEN+ to CLK− (Figure 6)7040Hold TimeD to CLK+(Figure 4)−525−575

0SYNC− to CLK−

CLK− to CKEN− (Figure 6)7545Minimum Pulse Width (Note 22)Data (D0−D7)SYNCCKEN

Random Clock Jitter (RMS)v fmax Typ

Input Differential Voltage Swing(Note 21)

Output Rise/Fall Times(20% − 80%)

150200145

ps

th

ps

tpw

tJITTERVPPtrtf

psmVps

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.21.VPP(min) is the minimum input swing for which AC parameters are guaranteed.22.The minimum pulse width is valid only if the setup and hold times are respected.

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MC10EP446, MC100EP446

CLK

DataSetup Time

DataValidtsth+ 0 −

Figure 4. Setup and Hold Time for Data

SYNCSYNCCLK

tsCLK

CKEN

CLKtSthFigure 5. Setup Time for SYNCFigure 6. Setup and Hold Time for CKEN

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MC10EP446, MC100EP446

APPLICATION INFORMATION

The MC10/100EP446 is an integrated 8:1 parallel to serialconverter. An attribute for EP446 is that the parallel inputsD0–D7 (Pins 17 – 24) can be configured to accept eitherCMOS, ECL, or TTL level signals by a combination ofinterconnects between VEF (Pin 27) and VCF (Pin 26) pins.For CMOS input levels, leave VEF and VCF open. For ECLoperation, short VCF and VEF (Pins 26 and 27). For TTLoperation, connect a 1.5 V supply reference to VCF and leavethe VEF pin open. The 1.5 V reference voltage to VCF pin canbe accomplished by placing a 1.5 kW or 500 W between VCFand VEE for 3.3 V or 5.0 V power supplies, respectively.

Note: all pins requiring ECL voltage inputs must have a50 W terminating resistor to VTT (VTT = VCC – 2.0 V).The CKSEL input (Pin 2) is provided to enable the user toselect the serial data rate output between internal clock datarate or twice the internal clock data rate. For CKSEL LOWoperation, the time from when the parallel data is latched ¬to when the data is seen on the SOUT ­ is on the falling edgeof the 7th clock cycle plus internal propagation delay(Figure 7). Note the PCLK switches on the falling edge ofCLK.

À

CLKD0D1D2D3D4D5D6D7

Number of Clock Cycles from Data Latch to SOUT1234567

D0−1D1−1D2−1D3−1D4−1D5−1D6−1D7−1

Data Latched

D0−2D1−2D2−2D3−2D4−2D5−2D6−2D7−2

Data Latched

D0−1D0−3D1−3D2−3D3−3D4−3D5−3D6−3D7−3

Data LatchedD1−1D2−1D3−1D4−1D5−1D6−1D7−1D0−4D1−4D2−4D3−4D4−4D5−4D6−4D7−4

Data LatchedD0−2D1−2D2−2D3−2D4−2D5−2D6−2SOUTCKSELPCLK

Á

Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW

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MC10EP446, MC100EP446

Similarly, for CKSEL HIGH operation, the time from when the parallel data is latched ¬ to when the data is seen on theSOUT ­ is on the rising edge of the 14th clock cycle plus internal propagation delay (Figure 8). Furthermore, the PCLK switcheson the rising edge of CLK.

ÀCLKD0D1D2D3D4D5D6D7

Data LatchedSOUTCKSELPCLK

D0−1D1−1D2−1D3−1D4−1D5−1D6−1D7−1

Data LatchedD0−1D0−2D1−2D2−2D3−2D4−2D5−2D6−2D7−2

Data LatchedD1−1D2−1D3−1D4−1D5−1D6−1D7−1D0−2D0−3D1−3D2−3D3−3D4−3D5−3D6−3D7−3

Number of Clock Cycles from Data Latch to SOUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Á

Figure 8. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH

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MC10EP446, MC100EP446

The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip–flops andclock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt serialdata bits are generated. The falling edge of the SYNC followed by a falling edge of CLK initiates the start of the conversionprocess on the next rising edge of CLK (Figures 9 and 10). As shown in the figures below, the device will start to latch theparallel input data after the a falling edge of SYNC ¬, followed by the falling edge CLK ­, on the next rising of edge of CLK® for CKSEL LOW

SYNC

(Synchronous ENABLE)

Number of Clock Cycles from Data Latch to SOUTSYNC(Asynchronous RESET)CLKSYNCD0D1D2D3D4D5D6D7

1234567ÁÀÂD0−1D0−2D1−2D2−2D3−2D4−2D5−2D6−2D7−2Data LatchedD0−1D1−1D2−1D3−1D0−3D1−3D2−3D3−3D4−3D5−3D6−3D7−3Data LatchedD4−1D5−1D6−1D7−1D0−2D1−2D2−2D3−2D0−4D1−4D2−4D3−4D4−4D5−4D6−4D7−4Data LatchedD4−2D5−2D6−2 D1−1D2−1D3−1D4−1D5−1D6−1D7−1Data LatchedSOUTCKSELPCLK

Figure 9. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC

SYNC

ÀÁCLK

ÂFigure 10. Synchronous Release of SYNC for CKSEL LOW

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MC10EP446, MC100EP446

For CKSEL HIGH, as shown in the timing diagrams below, the device will start to latch the parallel input data after the fallingedge of SYNC ¬, followed by the falling edge CLK ­, on the second rising edge of CLK ® (Figures 11 and 12).

SYNC

(Synchronous ENABLE)

SYNC(Asynchronous RESET)CLKSYNCD0D1D2D3D4D5D6D7

1Number of Clock Cycles from Data Latch to SOUT2345671011121314ÁÂÀD0−1D1−1D2−1D3−1D4−1D5−1D6−1D7−1Data LatchedD0−2D1−2D2−2D3−2D4−2D5−2D6−2D7−2Data LatchedD0−1D0−3D1−3D2−3D3−3D4−3D5−3D6−3D7−3Data LatchedD1−1D2−1D3−1D4−1D5−1D6−1D7−1D0−2D1−2D0−4D1−4D2−4D3−4D4−4D5−4D6−4D7−4SOUTCKSELPCLK

Figure 11. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH and SYNCSYNCÀÁCLKÂFigure 12. Synchronous Release of SYNC for CKSEL HIGH

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MC10EP446, MC100EP446

The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN willsuspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by thefalling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resumeall activities (Figure 13).

Internal ClockDisabled

Internal ClockEnabled

CLKCKENSOUTPCLKCKSEL

D0−1D1−1D2−1D3−1D4−1D5−1Figure 13. Timing Diagram with CKEN with CKSEL HIGH

The differential PCLK output (Pins 14 and 15) is a wordframer and can help the user synchronize the serial dataoutput, SOUT (Pins 11 and 12), in their applications.Furthermore, PCLK can be used as a trigger for inputparallel data (Figure 14).

An internally generated voltage supply, the VBB pin, isavailable to this device only. For single–ended input

conditions, the unused differential input is connected to VBBas a switching reference voltage. VBB may also rebias ACcoupled inputs. When used, decouple VBB and VCC via a0.01 mF capacitor and limit current sourcing or sinking to0.5 mA. When not used, VBB should be left open. Also, bothoutputs of the differential pair must be terminated (50 W toVTT) even if only one output is used.

CLK

RESET

CLKPattern GeneratorData Format Logic(FPGA, ASIC)PARALLELDATA OUTPUTPARALLELDATA INPUTSYNCEP446SOUTSERIAL DATATRIGGERPCLKFigure 14. PCLK as Trigger Application

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MC10EP446, MC100EP446

800CKSEL High700VOUTpp (mV)6005004003002001000CKSEL Low0500100015002000250030003500

INPUT CLOCK FREQUENCY (MHz)

Figure 15. Typical VOUTPP versus Input Clock Frequency, 255C

Figure 16. SOUT System Jitter Measurement

(Condition: 3.4 GHz input frequency, CKSEL HIGH, BEOFE32 bit pattern on SOUT

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MC10EP446, MC100EP446

QDriverDeviceQZo = 50 W50 W50 WDZo = 50 WDReceiverDeviceVTT

VTT = VCC − 2.0 V

Figure 17. Typical Termination for Output Driver and Device Evaluation(See Application Note AND8020/D − Termination of ECL Logic Devices.)

ORDERING INFORMATION

Device

MC10EP446FAMC10EP446FAGMC10EP446FAR2MC10EP446FAR2GMC100EP446FAMC100EP446FAGMC100EP446FAR2MC100EP446FAR2GMC10EP446MNGMC100EP446MNGMC10EP446MNR4GMC100EP446MNR4G

PackageLQFP−32LQFP−32(Pb−Free)LQFP−32LQFP−32(Pb−Free)LQFP−32LQFP−32(Pb−Free)LQFP−32LQFP−32(Pb−Free)QFN−32(Pb−Free)QFN−32(Pb−Free)QFN−32(Pb−Free)QFN−32(Pb−Free)

Shipping†250 Units / Tray250 Units / Tray2000 / Tape & Reel2000 / Tape & Reel250 Units / Tray250 Units / Tray2000 / Tape & Reel2000 / Tape & Reel74 Units / Rail74 Units / Rail1000 / Tape & Reel1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/DAN1406/DAN1503/DAN1504/DAN1568/DAN1672/DAND8001/DAND8002/DAND8020/DAND8066/DAND8090/D

−ECL Clock Distribution Techniques−Designing with PECL (ECL at +5.0 V)−ECLinPSt I/O SPiCE Modeling Kit−Metastability and the ECLinPS Family−Interfacing Between LVDS and ECL−The ECL Translator Guide−Odd Number Counters Design−Marking and Date Codes−Termination of ECL Logic Devices−Interfacing with ECLinPS

−AC Characteristics of ECL Devices

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MC10EP446, MC100EP446

PACKAGE DIMENSIONS

32 LEAD LQFPCASE 873A−02ISSUE C−T−, −U−, −Z−AEPVV1DETAIL YBASEMETAL32A1A254X0.20 (0.008)ABT−UZ1−T−BB18−U−17N9S8XM_RJG−AB−SEATINGPLANEDETAIL ADCESECTION AE−AE

−AC−0.10 (0.004)AC0.250 (0.010)HWXDETAIL ADKQ_GAUGE PLANENOTES:

1.DIMENSIONING AND TOLERANCINGPER ANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION:MILLIMETER.

3.DATUM PLANE −AB− IS LOCATED ATBOTTOM OF LEAD AND IS COINCIDENTWITH THE LEAD WHERE THE LEADEXITS THE PLASTIC BODY AT THEBOTTOM OF THE PARTING LINE.

4.DATUMS −T−, −U−, AND −Z− TO BEDETERMINED AT DATUM PLANE −AB−.5.DIMENSIONS S AND V TO BE

DETERMINED AT SEATING PLANE −AC−.6.DIMENSIONS A AND B DO NOTINCLUDE MOLD PROTRUSION.

ALLOWABLE PROTRUSION IS 0.250(0.010) PER SIDE. DIMENSIONS A ANDB DO INCLUDE MOLD MISMATCH ANDARE DETERMINED AT DATUM PLANE−AB−.

7.DIMENSION D DOES NOT INCLUDEDAMBAR PROTRUSION. DAMBAR

PROTRUSION SHALL NOT CAUSE THED DIMENSION TO EXCEED 0.520 (0.020).8.MINIMUM SOLDER PLATE THICKNESSSHALL BE 0.0076 (0.0003).

9.EXACT SHAPE OF EACH CORNERMAY VARY FROM DEPICTION.

DIMAA1BB1CDEFGHJKMNPQRSS1VV1WXMILLIMETERSMINMAX7.000 BSC3.500 BSC7.000 BSC3.500 BSC1.4001.6000.3000.4501.3501.4500.3000.4000.800 BSC0.0500.1500.0900.2000.4500.750_12 REF0.0900.1600.400 BSC1 _5 _0.1500.2509.000 BSC4.500 BSC9.000 BSC4.500 BSC0.200 REF1.000 REFINCHESMINMAX0.276 BSC0.138 BSC0.276 BSC0.138 BSC0.0550.0630.0120.0180.0530.0570.0120.0160.031 BSC0.0020.0060.0040.0080.0180.030_12 REF0.0040.0060.016 BSC1 _5 _0.0060.0100.354 BSC0.177 BSC0.354 BSC0.177 BSC0.008 REF0.039 REFhttp://onsemi.com

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0.20 (0.008)9−Z−S10.20 (0.008)ACT−UZFDM4XACT−UZDETAIL YAE元器件交易网www.cecb2b.com

MC10EP446, MC100EP446

PACKAGE DIMENSIONS

QFN32 5*5*1 0.5 PCASE 488AM−01

ISSUE ODPIN ONELOCATIONABENOTES:1.DIMENSIONS AND TOLERANCING PERASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.DIMENSION b APPLIES TO PLATEDTERMINAL AND IS MEASURED BETWEEN0.25 AND 0.30 MM TERMINAL4.COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.MILLIMETERSMINNOMMAX0.8000.9001.0000.0000.0250.0500.200 REF0.1800.2500.3005.00 BSC2.9503.1003.2505.00 BSC2.9503.1003.2500.500 BSC0.200−−−−−−0.3000.4000.5002 X

2 X0.15C0.15C0.10CTOP VIEW(A3)ASEATINGPLANE32 X0.08CL32 XSIDE VIEWA1C EXPOSED PAD16DIMAA1A3bDD2EE2eKL98D2K1732 XSOLDERING FOOTPRINT*5.303.200.6332 XE21243225b0.10CAB32 Xe3.205.300.05CBOTTOM VIEW32 X0.280.50 PITCH28 X*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: orderlit@onsemi.comN. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81−3−5773−3850ON Semiconductor Website: www.onsemi.comOrder Literature: http://www.onsemi.com/orderlitFor additional information, please contact your localSales Representativehttp://onsemi.com20MC10EP446/D