ADC-318资料

Full-Flash A/D Converter

FEATURES••••••••Low power dissipation (960mW max.)TTL compatible outputDiff./Integral nonlinearity (±½LSB max.)1:2 Demultiplexed straight output programmable2:1 Frequency divided TTL clock output with resetSurface mount packageSelectable Input Logic (TTl, ECL, PECL)+5V or ±5V Power Supply OperationINPUT/OUTPUT CONNECTIONSPIN1234567101112131415161718192021222324

FUNCTION

–DVs (Digital)

REF. BOTTOM (VRB)ANALOG GROUNDREF. MID POINT (VRM1)+AVS (Analog)ANALOG IN (VIN)

REF. MID POINT (VRM2)+AVS (Analog)

REF. MID POINT (VRM3)ANALOG GROUNDREF. TOP (VRT)

DIGITAL GROUND 3A/D CLOCK ECL/PECLA/D CLOCK ECL/PECLA/D CLOCK TTLNO CONNECTIONNO CONNECTIONNO CONNECTION+DVS2 (Digital)

DIGITAL GROUND 2B BIT 8 (LSB)B BIT 7B BIT 6B BIT 5

PIN4847454443424140393837363534333231302928272625

FUNCTION

RSET ECL/PECLRSET ECL/PECLRSET TTLSELECTINV

TTL CLOCK OUT +DVS2 (Digital)

DIGITAL GROUND 2A BIT 1 (MSB)A BIT 2A BIT 3A BIT 4A BIT 5A BIT 6A BIT 7

A BIT 8 (LSB)

DIGITAL GROUND 2+DVS2 (Digital)+DVS1 (Digital)

DIGITAL GROUND 1B BIT 1 (MSB)B BIT 2B BIT 3B BIT 4

GENERAL DESCRIPTIONThe ADC-318 and ADC-318A are 8 bit monolithic bipolar,full flash A/D converters. Though they have high, 120MHz(ADC-318) and 140MHz (ADC-318A), sampling rates, theirinput logic level, including the start convert pulse, is TTL,ECL and PECL compatible. Digital outputs are also TTLcompatible and allow a straight output or a programmable1:2 de-multiplexed output.The ADC-318 and ADC-318A feature ±1/2 LSB max.integral and differential non-linearity, +5V single or ±5V dualpower supply operation, a low 960mW maximum powerdissipation, 150MHz wide analog input range and excellenttemperature coefficient in a small 48 pin QFP package. Thestart convert pulse can have a 50% duty cycle.The ADC-318 and ADC-318A offer low cost, easy to usefunctionality for design engineers.VIN4 INV33 BIT 8 (LSB)VRT11688ATTLOUTPUT34 BIT 735 BIT 6ALATCH36 BIT 5 A OUTPUT37 BIT 438 BIT 339 BIT 26-BIT LATCHAND ENCODER40 BIT 1 (MSB)VRM396COMPARATORRESISTORMATRIXENCODERVRM27256621 BIT 8 (LSB)22 BIT 723 BIT 624 BIT 5 B OUTPUT25 BIT 426 BIT 327 BIT 228 BIT 1 (MSB)VRM14BLATCHVRB266BTTLOUTPUTA/D CLOCK ECL/PECL13A/D CLOCK ECL/PECL14A/D CLOCK TTL15DELAYDQQRSET ECL/PECL48RSET ECL/PECL47RSET TTL46SELECT43 CLOCK OUTTTL45 SELECTFigure 1. ADC-318/318A Functional Block Diagram

DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: (508) 339-3000, (800)233-2765 Fax: (508) 339-6356 • Email: sales@datel.com • Internet: www.datel.com

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®®ADC-318, ADC-318A

ABSOLUTE MAXIMUM RATINGSPARAMETERS

Supply Voltage (+AVS, +DVS, 1,2)Supply Voltage (AGND, DGND 1, 2)Supply Voltage (DGND 3)Supply Voltage (–DVS) 󰃀Supply Voltage (–DVS) 󰃁Reference Voltage (VRT)Reference Voltage (VRB)

Reference Voltage (VRT–VRB1)Input Voltage, analog (VIN)Input Voltage, digitalECLPECLTTL

Diff. Voltage between Pin 󰃂Power Dissipation, max. 󰃃

LIMITS–0.5 to +7.0–0.5 to +7.0–0.5 to +7.0–0.5 to +7.0–7.0 to +0.5+2.7 to +AVSVIN –2.7 to +AVS

2.5

VRT –2.7 to +AVS–DVS to +0.5–0.5 to DGND3–0.5 to +DVS1

2.72

UNITSVoltsVoltsVoltsVoltsVoltsVoltsVoltsVoltsVoltsVoltsVoltsVoltsW

DIGITAL INPUTSA/D Clock Pulse Width (TPW1)ADC-318ADC-318AA/D Clock Pulse Width (TPW0)ADC-318ADC-318ARSET Setup Time (Trs)RSET Hold Time (Trh)DIGITAL OUTPUTSOutput Voltage \"1\" (@–2mA)Output Voltage \"0\" (@1mA)Output Rise Time (Tr) 󰃃Output Fall Time (Tf) 󰃃Output Delay (Tdo1) 󰃄Output Delay (Tdo2) 󰃅Clockout Output Delay (Tdclk) 󰃆PERFORMANCEResolutionConversion Rate (fS)Straight ModeADC-318ADC-318ADe-multiplexed ModeADC-318ADC-318ASampling Delay (TdS)Aperture Jitter (Taj)Integral Linearity ErrorDiff. Linearity ErrorS/N Ratio 󰃇ADC-318(@fIN = 1kHz)(@fIN = 29.999MHz)ADC-318A(@fIN = 1kHz)(@fIN = 34.999MHz)Error RateADC-318(@fIN = 1kHz) 󰃈(@fIN = 29.999MHz)(@fIN = 24.999MHz)󰃉ADC-318A(@fIN = 1kHz) 󰃈(@fIN = 34.999MHz)(@fIN = 24.999MHz)󰃉POWER REQUIREMENTSDGND3–1.05DGND3–3.2

MIN.3.23.03.23.03.50TYP.——————MAX.——————UNITSnsnsnsnsnsnsFootnote:󰃀󰃁󰃂󰃃

Single SupplyDual Supply

A/D Clock–A/D Clock and RESET–RESET of ECL/PECL logic inputs.With ADC-318 mounted on a 50x50mm glass fiber baseepoxy board, 1.6mm thick.

2.4———1/Fc6.54.5——221/Fc+187—+0.5——1/Fc+2108VoltsVoltsnsnsnsnsns8——BitFUNCTIONAL SPECIFICATIONS(Typical at TA = 25°C, VRT = +4V, VRB = +2V, DGND3 = +DVS1= +DVS2 = +AVS =+5V, –DVS = 0V, PECL Logic, unless otherwise specified.)ANALOG INPUTSInput VoltageInput ResistanceInput Current

Input Capacitance 󰃀Input BandwidthVIN = 2Vp-p, –3dBREFERENCE INPUTSReference VoltageVRTVRB

VRT–VRB

Reference ResistanceReference CurrentVRT Offset VoltageVRB Offset VoltageDIGITAL INPUTSECL, PECL

Input Voltage \"1\"Input Voltage \"0\"Threshold VoltageInput Current \"1\" 󰃁Input Current \"0\" 󰃁Voltage DifferenceTTL

Input Voltage \"1\"Input Voltage \"0\"Threshold VoltageInput Current \"1\" 󰃂Input Current \"0\" 󰃂Select

Input Voltage \"1\"Output Voltage \"0\"Input Capacitance

——

DGND3–1.2

1001001001003———————4.510——————6—±0.5±0.5MHzMHzMHzMHznspsLSBLSB131313MIN.—40—150

TYP.+2 to +4——21—

MAX.—50500——

UNITSVoltskΩµApFMHz

————4040————dBdBdBdB+2.9+1.41.5759.722———11517.4——+4.1+2.62.1155281510VoltsVoltsVoltsΩmAmVmV

————————————10-1210-910-910-1210-910-9TPSTPSTPSTPSTPSTPS111111111111DGND3–0.5DGND3–1.4

—–50–750.4+2.0——–50–500———

——0.8——+1.5——+DVS1+DGND1—

—+500——+0.8—00——5

VoltsVoltsVoltsµAµAVoltsVoltsVoltsVoltsµAµA

pF

Supply VoltageOne Power Supply(+AVS, +DVS 1,2)One Power Supply (DGND3)One Power Supply (–DVS)Two Power Supply(+AVS, +DVS 1,2)Two Power Supply (DGND3)Two Power Supply (–DVS)ADC-318Supply Current (+IS)Supply Current (–IS)ADC-318ASupply Current (+zS)Supply Current (–zS)+4.75+4.75–0.05+4.75–0.05–5.51250.41100.4+5.0+5.00+5.00–5.01450.61500.6+5.25+5.25+0.05+5.25+0.05–4.751850.81850.8VoltsVoltsVoltsVoltsVoltsVoltsmAmAmAmA2元器件交易网www.cecb2b.com®®ADC-318, ADC-318A

POWER REQUIREMENTS (cont.)Power DissipationADC-318ADC-318APARAMETERSOperating Temp. Range, CaseADC-318, 318AThermal Impedanceθja12Storage Temperature RangePackage TypeWeight–20—–65—+75°C680570780790980960mWmW318A requires that the characteristic impedance of all input/output logic and analog input lines be properly matched.2.Power supply lines and grounding may effect the perfor-mance of the ADC-318 and ADC-318A. Separate andsubstantial AGND and DGND ground planes are required.These grounds have to be connected to one earth pointunderneath the device. There are three digital grounds,DGND1 (pin 29), DGND2 (pins 20, 32, 41) and DGND3 (pin12). These DGND 's are separated internally. DGND1 andDGND2 are always connected externally but DGND3 shallbe connected differently depending on whether the single ordual power supply mode is used, as explained later.The ADC-318 and ADC-318A have separate +AVs and+DVs pins. It is recommended that both +AVs and +DVs bepowered from a single source. Other external digital circuitsmust be powered with a separate +DVs. Layouts of +AVsand +DVs lines must be separated like the GND lines toavoid mutual interference and are connected to a pointthrough an LC filter. There are two digital supplies +DVs1(pin 30) and +DVs2 (pins 19, 31, 42). These are alsoseparated internally. These must be tied together outsidewhile in use. Bypassing all power lines with a 0.1uF ceramicchip capacitor and the use of multilayered PC boards isrecommended.3.The analog input terminal (pin 6) has 21pF of input capaci-tance. The input signal has to be given via a buffer amplifierwhich has enough driving power. Make lead wires as shortas possible and use chip resistors and capacitors to avoidparasitic capacitance and inductance.4.The use of a buffer amplifier and bypass capacitors is alsorecommended on the reference input terminals VRT (pin 11)and VRB (pin 2). The analog input range is determined by5V(A)+10µF10µF10µH62.5—°C/Watt—+150°C48-pin, plastic QFP0.25 ounces (0.7 grams)Footnotes:󰃀VIN = +3V +0.07Vrms󰃁VIH = DGND3–0.8VVIL = DGND3–1.6V󰃂VIH = 3.5VVIL = 0.2V

󰃃TTL, 0.8 to 2.0V, CL = 5pF

󰃄DMUX Mode, CL = 5pF; FC = Clockfrequency

󰃅󰃆󰃇󰃈󰃉

1112Straight Mode, CL = 5pFCL = 5pF

VIN = FS, DMUX mode

VIN = FS, DMUX mode, Error >16LSBVIN = FS, Straight mode, Error >16LSB\"Times Per Sample\"

Mounted on 50x50mm, 1.6mm thickglass fiber base epoxy board

TECHNICAL NOTES1.The ADC-318 and ADC-318A are ultra high speed full flashA/D converters that have 120MHz and 140MHz samplingrates respectively. The ADC-318 and ADC-318A are fullyinterchangeable products with the exception of theirsampling rates. Their inputs are TTL, ECL and PECLcompatible and their outputs are TTL compatible. Obtainingfully specified performance from the ADC-318 and ADC-5V(A)10µF10µH5V(D)5V(D)+10µF++5VRB+2V10µF81219303142MSB40 A BIT 139 A BIT 238 A BIT 337 A BIT 436 A BIT 5VRB+2V10µF5819303142MSB40 A BIT 139 A BIT 238 A BIT 337 A BIT 436 A BIT 52+2+ANALOG IN+2V to +4V35 A BIT 67934 A BIT 733 A BIT 8LSBMSB28 B BIT 127 B BIT 226 B BIT 325 B BIT 424 B BIT 523 B BIT 61513144843444531012029324122 B BIT 721 B BIT 8LSB TTLCLOCK OUT5V(D)ANALOG IN+2V to +4V35 A BIT 67934 A BIT 733 A BIT 8LSBMSB28 B BIT 127 B BIT 226 B BIT 325 B BIT 424 B BIT 523 B BIT 61522 B BIT 721 B BIT 8LSB 43444531011220293241TTLCLOCK OUT5V(D)VRT+4V10µFTTL11+ADC-318ADC-318AVRT+4V10µF11+ADC-318ADC-318AA/D CLOCKECLA/D CLOCKA/D CLOCK1314484746PECL47465V(D)5V(D)+10µF5V(D)Figure 2-1: One Power Supply Operation (TTL, PECL)Figure 2-2: Two Power Supply Operation (ECL)

Note: All capacitors not otherwise designated are 0.1µF

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®®ADC-318, ADC-318A

the reference input voltages given to VRT and VRB. Keepthe ranges of V within values shown in this data sheet.Standard settings are VRT = +4.0V, V input range from+2 to +4V. This setting can be varied to VRT = +3.5V,VRB = +2V and 1.5V p-p analog input range, dependingon your selection of amplifiers which may provide lessthan +4V output.5.The ADC-318 and ADC-318A have resistor matrix taps atVRM1 (pin 4), VRM2 (pin 7) and VRM3 (pin 9). These pinsprovide ¼, ½ and ¾ full scale of VRT-VRB voltage respec-tively. These outputs may be used to adjust the integralnon-linearity. Bypass these pins to GND with 0.1uF ceramicchip capacitors.6.A/D CLK input and RSET/RSET inputs are TTL or ECL,PECL (Positive ECL) compatible. Pins are providedindividually. TTL or PECL is available with +5V single powerapplied. ECL is available with ±5V dual power applied. Theconnections of –DVs (pin 1) and DGND3 (pin12) aredifferent depending on the power supply mode used. Referto Figures 2-1 and 2-2.a.For +5V single power (TTL or PECL) –DVs (pin 1) isconnected to DGND. DGND3 (pin 12) is connectedto +5V power.b.For ±5V dual power (ECL) –DVs (pin 1) is connectedto –5V power. DGND3 (pin 12) is connected to DGND.7.When the A/D CLK is driven with ECL or PECL, A/D CLK(pin 13) and A/D CLK (pin 14) are to be driven by differen-tial logic inputs to avoid unstable performance at criticallyhigh speeds. If a risk of unstable performance is accept-able, single logic input can be used opening A/D CLK (pin14). The A/D CLK pin should be bypassed to DGND with a0.1uF ceramic capacitor. When connected this way therewill be a voltage of DGND –1.2V on the A/D CLK pin. Thisvoltage can not be used as a threshold voltage for ECL orPECL. Input the A/D CLK pulse to pin 15 when TTL isselected.8.The ADC-318 and ADC-318A have RSET/RSET input pins.An internal frequency half divider can be initialized withinputs to these pins. With ECL or PECL, differential inputsare given to RSET (pin 48) and RSET (pin 47). Thisfunction can be achieved with a single input, leaving pin 47open and bypassing to DGND with a 0.1uF ceramic chipcapacitor. The voltage level of pin 47 is the thresholdvoltage of ECL or PECL. Use RSET (pin 46) for TTL.9.SELECT (pin 45) is used to set output mode. Connection ofthis pin to DGND selects the straight output mode andconnection to +DVs selects the 1:2 de-multiplexed outputmode. The maximum sampling rates are 100MHz for straightmode (For both models, ADC-318 and ADC-318A) and120MHz (ADC-318) and 140MHz (ADC-318A) for de-multiplexed mode. Refer to figure 2-4. There is an applica-tion where a multiple number of ADC-318/318A's are usedwith a common A/D CLK and outputs are in de-multiplexedmode. In this case, the initial conditions of the frequency halfdivider of each A/D Converter are not synchronized and it ispossible that each converter may have one clock maximumof timing lag. This lag can be avoided by giving a commonRSET pulse to all converters at power ON. (See Figure 3-3and 3-4, timing diagrams.)10.The ADC-318 and ADC-318A have a TTL compatible CLKOUT (pin 43). Since the rising edge of this pulse can provideSetup and Hold time of output data, regardless of the outputmode, this signal can be used as synchronization pulse forexternal circuits. Data output timing is different for thestraight mode and the de-multiplexed mode. See the timingchart Figure 3.11. INV (pin 44) is used to invert polarity of the TTL compatibleoutput data from both A and B ports. Leaving this pin openor connected to +DVs makes the output positive true andconnection to DGND makes it negative true logic. Seeinput/output code table, Table 4.Table 3: Logic Input Level vs. Power Supply Settings

DIGITAL INPUTLEVELTTLPECLECL–DVS0V0V–5VDGND3+5V+5V0VSUPPLYVOLTAGES+5V+5V±5VTable 4: Digital Output Coding

SIGNALINPUTVOLTAGEVRTVRM2VRBDIGITAL OUTPUT CODE (A,B OUTPUT)INV=1INV=0LSBMSBLSBMSB11111111100000000111111100000000000000000111111110000000 11111111A/D CONVERSION MODE5V(D)DEMULTIPLEXED DATA OUTSTRAIGHT DATA OUTTTL LEVEL RESET INPUT1112ADC-318ADC-318A

OUTPUT CODINGRSET5V(D)131415161718TTL LEVEL CLOCK INPUT

RSETSTRAIGHT BINARYCOMPLEMENTARY BINARYA/D CLOCK

RSETTTL CLOCK OUTA/D CLOCKA/D CLOCK

ECL, PECL LEVELRESET INPUTS1484745444342ECL, PECL LEVEL CLOCK INPUTS

2ADC-318ADC-318AFigure 2-3: A/D Clock Input ConnectionFigure 2-4: Digital Input/Output Connections

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3ns min. 6ns maxN-1ANALOG SIGNAL AIN

TPW1A/D CLOCKTPW0A DATA OUTPUTB DATA OUTPUTTd clock 4.5ns min. 8ns max.CLOCK OUTTrhRSET0ns min.Trs3.5ns min.Trh2.0VTdsNN+2N+1N+3N+4N+5N+6N+7TTdo2N+12.0V0.8V2.0V0.8V6.5ns min. 10ns max.N+3N+2NTdo1T+2ns max.2.0V0.8V~T~T318 318ATPW1, min 3.2ns 3.0ns TPW0, min 3.2ns 3.0ns RESET PERIODTrs0.8VFigure 3-1: Demultiplexed Data Output (Select-Pin: +DVS or left open, 120MHz max. Clock Frequency)

TdsN-13ns min. 6ns max.NN+2N+1N+3318 318ATPW1, min 3.2ns 3.0ns TPW0, min 3.2ns 3.0ns ANALOG SIGNAL AIN

TPW1A/D CLOCKTTPW0A DATA OUTPUTB DATA OUTPUTN-42.0V0.8V2.0V0.8VN-3N-2N-1NN-5N-46.5ns min. 10ns max. N-3N-2N-1Tdo2CLOCK OUT(inverted A/D CLOCK OUT)2.0V0.8VTd clockRSET4.5ns min. 8ns max.Figure 3-2: Straight Data Output (Select-Pin: DGND, 100MHz max. Clock Frequency)

A/D CLOCKA/D CLOCKRSETCLOCK OUT 1CLOCK OUT 1DATA OUT 1(A,B)DATA OUT 1(A,B)CLOCK OUT 2CLOCK OUT 2DATA OUT 2(A,B)DATA OUT 2(A,B)A/D CLOCKA/D CLOCKADC-318/318ARSET(1)CLOCK OUT 188CLOCK OUT 2(2)88DATA 2 (A, B)DATA 1 (A, B)A/D CLOCKA/D CLOCKADC-318/318ARSET(1)CLOCK OUT 188CLOCK OUT 2(2)88DATA 2 (A, B)DATA 1 (A, B)A/D CLOCKADC-318/318AA/D CLOCKRSETA/D CLOCKADC-318/318ARSETA/D CLOCKRSETFigure 3-3: Parallel Operation without RSET PulseFigure 3-4: Parallel Operation using RSET Synchronization

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®®ADC-318, ADC-318A

APPLICATIONThis device can be used in applications where 3 parallelchannels are synchronized. Conversion speed is the highestin the de-multiplexed mode. It is difficult to control timing ofthree channels at such a high speed. Two practical ways tomaintain timing for reading data into the system are given.1.Clock output of one A/D is used in reading data ofother channelsTime delay of Clock Output and Output Data arespecified as:Td clk (CLK OUT Delay) ; 4.5nSec min., 8.0nsec max.Tdo2 (Output Data Delay); 6.5nSec min., 10nsec max.These values apply over the operating temperature andsupply voltage ranges. Timing control of Tset (Setup Time)seems to be very critical. It tends to lead by 0.5nsec astemperature and supply voltages go lower. When A/Dconverters for 3 channels are used on the same board,temperature and supply voltages tend to change in thesame direction and effects caused by these changesare negligible.Tdclk and Tdo2 at Ta=25°C , +Vs=+5.0V are;Td clk: 5.0nsec min., 7.5nsec max.Tdo2: 7.0nsec min., 9.5nsec max.So long as devices are located on the same board and takepower from the same source, 2.5nsec min. of setup time fordata reading can be secured even though temperature andpower supply voltages vary. A timing diagram at 140MHzsampling rate is shown in Figure 4a.2.To read output data of 3 channels into a gate arrayBoth output data lines and each clock output are read into agate array if the digital circuits after the A/D conversionconsist of one high speed gate array. An AND gate isprepared to take the AND of each output signal which isused for reading output data. The slowest rise time clockdetermines the system clock. Thus adequate setup time issecured. This method can be employed only when a highspeed gate array is used. The setup time is delayed by thedelay time of the AND gate. The use of a discrete IC gate isnot recommended because of its time delay characteristics.See Figure 4bA/D CLCKTh resetRSET5.0nS(4.5nS)Td clck min.7.5nS(8.0nS)CLK OUTTd clck max.7.0nS(6.5nS)9.5nS(10nS)Tset min. 2.5nSTdo2 min.Tdo2 max.OUTPUTDATA (A, B)*Values in parenthesis are forthe entire operating temperatureand operating power supply ranges

Thold min. 6.5ns14nSFigure 4a: Timing diagram 1

A/D CLCKTh resetRSET5.0nS(4.5nS)Td clck min.7.5nS(8.0nS)7.0nS(6.5nS)9.5nS(10nS)14nSCLK OUTTd clck max.Tdo2 min.Tdo2 max.OUTPUTDATA (A, B)*Values in parenthesis are forthe entire operating temperatureand operating power supply rangesGATE ARRAY CLK(CLK OUT 1, CLK OUT 2, CLK OUT 3)Tset min. 5.0nS+XnSThold min. 6.5nS–XnSFigure 4b: Timing diagram 2

6元器件交易网www.cecb2b.com®®Figure 5: Evaluation Circuit Diagram

7ADC-318, ADC-318A

1.The evaluation circuit shown employs PECL logic. Because of this, a 1Vp- p, 0V center, sine wave must be used asthe clock input (A/ D CLK) at CN3.2.When analog signals are taken from the CN1 amplifier input “A” must be left open while “B” is short circuited. Theanalog input signals at CN1 must be less than 800mVp- p, 0V and zero centered. The +AMP and –AMP supply pinson the input amplifier are normally connected to +/- 5V which, along with the gain of -2 used with the CLC- 404 in thiscircuit, will limit the amplifiers output dynamic range. To increase the amplifiers output dynamic range the +AMP pincan be connected to +7V and the –AMP connected to -3V. V RT and V RB may require adjustment in this case.3.When analog signals are input from CN2, the direct input, AC coupling can be achieved by inserting a 0.1µFcapacitor at” A” and a 10kOhm resistor at “B”. It is not necessary to be concerned about the output voltage of theinput amplifier. V RT may be limited in this case by NJM3403. The input voltage to the NJM3403 amplifier can beadjusted to correct. Both V RT and V RB can be trimmed.元器件交易网www.cecb2b.com

ADC-318, ADC-318A

ADC-318 ADC-318A ADC-318A ADC-318 ADC-318 ADC-318Afin = Fc/4–1KHzError> 16LSB

Fig. 4-6: Allowable Ambient Temperature vs. Air Flow°C90Analog Input Current (µA)Fig. 4-7: Analog Input Current vs.Voltage InputsFig. 4-8: Maximum Conversion Rate vs.Temperature170

VRT = +4VVRB = +2V

100

Conversion Rate (MHz)Four-layer boardSNR+THD (dB)80Double-layer board70Single-layer board600123m/s200

160150140

ADC-318: FC=120MHzADC-318A: FC=140MHz ADC-318A ADC-318130

0

2

3

4

–25

25

75

VIN Pin Voltage (V)Fig. 4-9: Sine Wave Curvefit Test1.0000(256)0.5000(192)VOLT/ (CODE)0.0000(128)–0.500()

Sine Wave Curvefit Test

876543210–1–2–3–4–5–6–7–8

TA –Ambient Temperature (°C)DEVIATION (LSB)S/N Ratio 48.7dB7.8 Effective Bits

Conditions

Sampling Frequency 120MHzSignal Frequency 996kHz4096 Points

DS-0358 5/98

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356Internet: www.datel.com Email: sales@datel.comData sheet fax back: (508) 261-2857

DATEL (UK) LTD. Tadley, England Tel: (01256)-880444

DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01DATEL GmbH Munchen, Germany Tel: -544334-0

DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025

DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained hereindo not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.