HT82V26A资料

HT82V26A

16-BitCCD/CISAnalogSignalProcessor

TechnicalDocument

·ToolsInformation·FAQs

·ApplicationNote

Features

·Operating voltage: 5V (Typ.)

·Low power consumption at 400mW (Typ.)·Power-downmode:Under2mA(Typ.)·16-bit30MSPSA/Dconverter·Guaranteedwon¢tmisscodes·1~6programmablegain·CorrelatedDoubleSampling·±250mVprogrammableoffset·Inputclampcircuitry

·Internalvoltagereference

·Multiplexedbyte-wideoutput(8+8format)·Programmable3-wireserialinterface·3V/5VdigitalI/Ocompatibility·3-channeloperationupto30MSPS

·2-channel(Even-Odd)operationupto30MSPS·1-channeloperationupto25MSPS

·28-pinSSOP/SOPpackage(lead-freeonrequest)

Applications

FlatbeddocumentscannersFilmscanners

DigitalcolorcopiersMultifunctionperipherals

GeneralDescription

TheHT82V26AisacompleteanalogsignalprocessorforCCDimagingapplications.Itfeaturesa3-channelarchitecturedesignedtosampleandconditiontheout-putsoftri-linearcolorCCDarrays.Eachchannelcon-sistsofaninputclamp,CorrelatedDoubleSampler(CDS),offsetDACandProgrammableGainAmplifier(PGA),andahighperformance16-bitA/Dconverter.TheCDSamplifiersmaybedisabledforusewithsen-sorssuchasContactImageSensors(CIS)andCMOSactivepixelsensors,whichdonotrequireCDS.

The16-bitdigitaloutputismultiplexedintoan8-bitout-putwordthatisaccessedusingtworeadcycles.Thein-ternalregistersareprogrammedthrougha3-wireserialinterface,whichprovidesgain,offsetandoperatingmodeadjustments.

TheHT82V26Aoperatesfromasingle5Vpowersupply,typicallyconsumes400mWofpower.

Rev.1.001August16,2005

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HT82V26A

BlockDiagram

PinAssignment

Rev.1.002August16,2005

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HT82V26A

PinDescription

PinNo.1234567~1415161719,2718,2820212223242526

PinNameCDSCLK1CDSCLK2ADCCLKOEDRVDDDRVSSD7~D0SDATASCLKSLOADAVSSAVDDREFBREFTVINBCMLVINGOFFSETVINR

I/ODIDIDIDIPPDODI/DODIDIPPAOAOAIAOAIAOAI

Description

CDSreferenceclockpulseinputCDSdataclockpulseinput

A/Dsampleclockinputfor3-channelsmodeOutputenable,activelowDigitaldriverpowerDigitaldrivergroundDigitaldataoutputSerialdatainput/outputClockinputforserialinterfaceSerialinterfaceloadpulseAnaloggroundAnalogsupplyReferencedecouplingReferencedecouplingAnaloginput,blueInternalreferenceoutputAnaloginput,greenClampbiasleveldecouplingAnaloginput,red

AbsoluteMaximumRatings

SupplyVoltage..........................VSS-0.3VtoVSS+5.5VInputVoltage.............................VSS-0.3VtoVDD+0.3V

StorageTemperature...........................-50°Cto125°COperatingTemperature..........................-25°Cto75°C

Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder²AbsoluteMaximumRatings²may

causesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliabil-ity.

D.C.Characteristics

SymbolLogicInputsVIH

HighLevelInputVoltage

(CDSCLK1,CDSCLK2,ADCCLK,OE,SCK,SLOAD)

LowLevelInputVoltage(CDSCLK1,CDSCLK2,ADCCLK,OE,SCK,SLOAD)

HighLevelInputVoltage(SDATA)LowLevelInputVoltage(SDATA)HighLevelInputCurrentLowLevelInputCurrentInputCapacitance

¾

¾

2

¾

¾

V

Parameter

TestConditionsVDD

Conditions

Min.

Typ.

Max.

Unit

VILVIH1VIL1IIHIILCINRev.1.00

¾¾¾¾¾¾

3

¾¾¾¾¾¾

¾2.5¾¾¾¾

¾¾¾101010

0.8¾1.5¾¾¾

VVVmAmApF

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HT82V26A

SymbolLogicOutputsVOHVOLIOHIOL

HighLevelOutputVoltage(SDATA,D0~D7)LowLevelOutputVoltage(SDATA,D0~D7)HighLevelOutputCurrentLowLevelOutputCurrent

¾¾¾¾

¾¾¾¾

DRVDD-0.5

¾¾¾

¾¾11

¾0.5¾¾

VVmAmA

Parameter

TestConditionsVDD

Conditions

Min.

Typ.

Max.

Unit

A.C.Characteristics

SymbolPowerSuppliesVADDVDRDDtMAX3tMAX2tMAX1

AVDDDRVDD

3-channelModewithCDS2-channelModewithCDS1-channelModewithCDSADCResolutionIntegralNonlinear(INL)DifferentialNonlinear(DNL)OffsetErrorGainError

AnalogInputsRFSViCiIi

Amplifiers

PGAGainatMinimumPGAGainatMaximumPGAGainResolution

ProgrammableOffsetatMinimumProgrammableOffsetatMaximumOffsetResolution

TemperatureRangetAPtot

Operating

TotalPowerConsumption

¾¾

¾¾

0¾

¾400

70¾

°CmW

PowerConsumption

¾¾¾¾¾¾

¾¾¾¾¾¾

¾¾¾¾¾¾

15.856-2502509

¾¾¾¾¾¾

V/VV/VBitsmVmVBits

Full-scaleInputRangeInputLimitsInputCapacitanceInputCurrent

¾¾¾¾

¾¾¾¾

¾AVSS-0.3¾¾

2.0¾1010

¾AVDD+0.3

¾¾

Vp-pVpFnA

¾¾¾¾¾¾¾¾¾¾

¾¾¾¾¾¾¾¾¾¾

4.753303025¾¾-1-100¾

55¾¾¾16±32¾¾5

5.255.25¾¾¾¾¾1100¾

VVMSPSMSPSMSPSBitsLSBLSBmV%FSR

Parameter

TestConditionsVDD

Conditions

Min.

Typ.

Max.

Unit

MaximumConversionRate

Accuracy(EntireSignalPath)

Rev.1.004August16,2005

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HT82V26A

TimingSpecificationSymbol

ClockParameterstPRAtPRBtPRCtADCLKtC1tC2tC1C2tADC1tADC2tADtaC2C1taC2ADRtbC2ADRtbC1ADRtbC2C1tcC2C1tcC1ADFtcC2ADRfSCLKtLStLHtDStDHtRDV

DataOutputtOD

OutputDelay

Latency(PipelineDelay)

¾¾

¾¾

nsCycles

3-channelpixelrate

2-channel(Even-Odd)pixelrate1-channelpixelrateADCCLKPulseWidthCDSCLK1PulseWidthCDSCLK2PulseWidth

CDSCLK1FallingtoCDSCLK2RisingADCCLKRisingtoCDSCLK1FallingADCCLKRisingtoCDSCLK2FallingAnalogSamplingDelay

CDSCLK2FallingtoCDSCLK1RisingCDSCLK2FallingtoADCCLKRisingCDSCLK2FallingtoADCCLKRisingCDSCLK1RisingtoADCCLKRisingCDSCLK2FallingtoCDSCLK1RisingCDSCLK2FallingtoCDSCLK1RisingCDSCLK1RisingtoADCCLKFallingCDSCLK2FallingtoCDSCLK1RisingMaximumSCLKFrequencySLOADtoSCLKSetupTimeSCLKtoSLOADHoldTimeSDATAtoSCLKRisingSetupTimeSCLKRisingtoSDATAHoldTimeFallingtoSDATAValid

100601612120005303030151515020101010101010

¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾

¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsMHznsnsnsnsns

Parameter

Min.

Typ.

Max.

Unit

3-ChannelModeOnly

2-ChannelModeOnly

1-ChannelModeOnly

SerialInterface

Rev.1.005August16,2005

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HT82V26A

FunctionalDescription

IntegralNonlinear(INL)

Integralnonlinearerrorreferstothedeviationofeachin-dividualcodefromalinedrawnfromzeroscalethroughapositivefullscale.Thepointusedaszeroscaleoccurs1/2LSBbeforethefirstcodetransition.Apositivefullscaleisdefinedasalevel1/2LSBbeyondthelastcodetransition.Thedeviationismeasuredfromthemiddleofeachparticularcodetothetruestraightline.DifferentialNonlinear(DNL)

AnidealADCexhibitscodetransitionsthatareexactly1LSBapart.DNListhedeviationfromthisidealvalue.Thuseverycodemusthaveafinitewidth.Nomissingcodesguaranteedforthe16-bitresolutionindicatesthatallthe65536codesrespectively,arepresentintheover-alloperatingrange.OffsetError

ThefirstADCcodetransitionshouldoccuratalevel1/2LSBabovethenominalzeroscalevoltage.InternalRegisterDescriptionsRegisterNameConfiguration

AddressA20

A10

A00

D80

D70

D61

D53-CH

D4CDSon

DataBits

D3ClampVoltageDelayenable

D2EnablePowerDown

D1OutputDelay

D01byteout

Theoffseterroristhedeviationoftheactualfirstcodetransitionlevelfromtheideallevel.GainError

Thelastcodetransitionshouldoccurforananalogvalueof1/2LSBbelowthenominalfull-scalevoltage.Gainerroristhedeviationoftheactualdifferencebe-tweenthefirstandthelastcodetransitionsandtheidealdifferencebetweenthefirstandthelastcodetransi-tions.

ApertureDelay

TheaperturedelayisthetimedelaythatoccurswhenasamplingedgeisappliedtotheHT82V26Auntiltheac-tualsampleoftheinputsignalisheld.BothCDSCLK1andCDSCLK2sampletheinputsignalduringthetransi-tionfromhightolow,sotheaperturedelayismeasuredfromeachclock¢sfallingedgetotheinstanttheactualinternalsampleistaken.

MUXRedPGAGreenPGABluePGARedOffsetGreenOffsetBlueOffset

0001111

0110011

1010101

0000MSBMSBMSB

RGB/

RedGreenBlue

BGR000

000

MSBMSBMSB

CDSCLK1CDSCLK2ADCCLKdelaydelaydelay

LSBLSBLSBLSBLSBLSB

InternalRegisterMap

ConfigurationRegister

TheconfigurationregistercontrolstheHT82V26A¢soperatingmodeandbiaslevels.BitsD6shouldalwaysbesethigh.

BitD5willconfiguretheHT82V26Aforthe3-channel(high)modeofoperation.SettingthebitD4highwillenabletheCDSmodeofoperation,andsettingthisbitlowwillenabletheSHAmodeofoperation.

BitD3setsthedcbiasleveloftheHT82V26A¢sinputclamp.Thisbitshouldalwaysbesethighforthe4Vclampbias,unlessaCCDwitharesetfeedthroughtransientexceeding2Visused.SettingthebitD3low,theclampvoltageis3V.BitD2controlsthepower-downmode.SettingbitD2highwillplacetheHT82V26Aintoaverylowpower²sleep²mode.AllregistercontentsareretainedwhiletheHT82V26Aisinthepower-downstate.SettingbitD1highwillconfiguretheHT82V26Aforthedigitaloutput(D0~D7)delay2ns.BitD0controlstheoutputmodeoftheHT82V26A.SettingbitD0highwillenableasinglebyteoutputmodewhereonly8MSBsofthe16bADCisoutput.IfbitD0issetlow,thenthe16bADCoutputismultiplexedintotwobytes.

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HT82V26A

D8

D7

D6

D5

D4

D3

D2

D1

D0

3channelsCDSoperationClampbiasPower-down

Setto0Setto0Setto1

1=On*0=Off

1=CDSmode*1=4V*0=SHAmode

0=3V

1=On

1byteout

Outputdelay(High-byte

only)1=On

1=On0=Off*

0=Off(Normal)*0=Off*

ConfigurationRegisterSettings

Note:*Power-ondefaultvalueMUXRegister

TheMUXregistercontrolsthesamplingchannelorderandthe2-channelmodeconfigurationintheHT82V26A.BitsD8shouldalwaysbesetlow.BitD7isusedwhenoperatinginthe3-channelmodeorthe2-channelmode.SettingbitD7highwillsequencetheMUXtosampletheredchannelfirst,thenthegreenchannel,andthenthebluechannel.Wheninthe3-channelmode,theCDSCLK2risingedgealwaysresetstheMUXtosampletheredchannelfirst(seetimingdiagrams).WhenbitD7issetlow,thechannelorderisreversedtobluefirst,greensecond,andredthird.TheCDSCLK2risingedgewillalwaysresettheMUXtosamplethebluechannelfirst.BitsD6,D5andD4areusedwhenoperatingin1or2-channelmode.BitD6issethightosampletheredchannel.BitD5issethightosamplethegreenchannel.BitD4issethightosamplethebluechannel.TheMUXwillremainstationaryduring1-channelmode.Thetwochannelmodeisselectedbysettingtwoofthechannelselectbits(D4~D6)high.TheMUXsamplesthechannelsintheorderselectedbybitD7.BitsD0~D3areusedforcontrollingCDSCLK1,CDSCLK2andADCCLKinternaldelay.

D8

D7MUXOrder

Setto01=R-G-B*

0=B-G-R

D6

D5ChannelSelect

1=RED*1=GREEN0=Off0=Off*

1=BLUE

0=Off*D4

D30=Off1=On*

D20=2ns*1=4ns

D10=2ns*1=4ns

D00=0ns*1=2ns

EnableDelayCDS1Delay

CDS2DelayADCKDelay

MUXRegisterSettings

Note:*Power-ondefaultvaluePGAGainRegisters

TherearethreePGAregistersforuseinindividuallyprogrammingthegaininthered,greenandbluechannels.BitsD8,D7andD6ineachregistermustbesetlow,andbitsD5throughD0controlthegainrangeinincrements.SeefigureforagraphofthePGAgainversusPGAregistercode.ThecodingforthePGAregistersisastraightbinary,withanallzerowordscorrespondingtotheminimumgainsetting(1x)andanallonewordcorrespondingtothemaximumgainsetting(5.85x).

TheHT82V26AusesoneProgrammableGainAmplifier(PGA)foreachchannel.EachPGAhasagainrangefrom1x(0dB)to5.85x(15.3dB),adjustableinsteps.TheFigureshowsthePGAgainasafunctionofthePGAregistercode.AlthoughthegaincurveisapproximatelylinearindB,thegaininV/Vvariesinnonlinearproportionwiththeregister

5.85

code,accordingtothefollowingtheequation:Gain=

63-G1+4.85x()

63WhereGisthedecimalvalueofthegainregistercontents,andvariesfrom0to63.

PGAGainTransferFunction

Rev.1.00

7

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HT82V26A

D8Setto000

D7Setto000

D6Setto000

D5MSB00

00

00...11

00

00

D4

D3

D2

D1

D0LSB0*1

1.01.013...5.435.85

0.00.12...14.715.3

Gain(V/V)

Gain(dB)

0000001111111101

PGAGainRegisterSettings

Note:*Power-ondefaultvalueOffsetRegisters

Therearethreeoffsetregistersforuseinindividuallyprogrammingtheoffsetinthered,green,andbluechannels.BitsD8throughD0controltheoffsetrangefrom-250mVto250mVin512increments.

Thecodingfortheoffsetregistersissignmagnitude,withD8asthesignbit.TheTableshowstheoffsetrangeasafunctionofthebitsD8throughD0.

D8MSB00

00

00

00

00

00...100...1

00

00

D7

D6

D5

D4

D3

D2

D1

D0LSB0*1

00.98...2500-0.98...-250Offset(mV)

011100100100100100100101

11111111

Note:*Power-ondefaultvalue

TimingDiagrams

SerialWriteOperationTiming

SerialReadOperationTiming

Rev.1.008August16,2005

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HT82V26A

3-ChannelCCDModeTiming(SelectR-G-BMode)

2-ChannelCCDModeTiming(SelectG-BMode)

Rev.1.009August16,2005

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HT82V26A

1-ChannelCCDModeTiming

3-ChannelSHAModeTiming(SelectR-G-BMode)

Rev.1.0010August16,2005

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HT82V26A

2-ChannelSHAModeTiming(SelectG-BMode)

1-ChannelSHAModeTiming

Rev.1.0011August16,2005

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HT82V26A

ApplicationCircuits

Therecommendedcircuitconfigurationforthe3-channelCDSmodeoperationisshowninthefigurebelow.Therec-ommendedinputcouplingcapacitorvalueis0.1mF.

AsinglegroundplaneisrecommendedfortheHT82V26A.AseparatepowersupplymaybeusedforDRVDD,thedigi-taldriversupply,butthissupplypinshouldstillbedecoupledtothesamegroundplaneaswiththerestoftheHT82V26A.Theloadingofthedigitaloutputsshouldbeminimized,eitherbyusingshorttracestothedigitalASIC,orbyusingexternaldigitalbuffers.Tominimizetheeffectofdigitaltransientsduringmajoroutputcodetransitions,thefallingedgeoftheCDSCLK2shouldoccurincoincidencewithorbeforetherisingedgeofADCCLK.All0.1mFdecouplingca-pacitorsshouldbelocatedascloseaspossibletotheHT82V26Apins.Whenoperatinginasinglechannelmode,theunusedanaloginputsshouldbegrounded.

Note:

Forthe3-channelSHAmode,alloftheaboveconsiderationsalsoapplyforthisconfiguration,exceptthattheanaloginputsignalsaredirectlyconnectedtotheHT82V26Awithouttheuseofcouplingcapacitors.TheOFF-SETpinshouldbegroundediftheinputstotheHT82V26Aaretobereferencedtoground,oraDCoffsetvolt-ageshouldbeappliedtotheOFFSETpininthecasewhereacoarseoffsetneedstoberemovedfromtheinputs.Theanaloginputsignalsmustalreadybedc-biasedbetween0Vand2V,ifOFFSETisconnectedtoground.

Rev.1.0012August16,2005

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HT82V26A

PackageInformation

28-pinSSOP(209mil)OutlineDimensions

SymbolABCC¢DEFGHa

Dimensionsinmil

Min.291196939665¾420°

Nom.¾¾¾¾¾25.59¾¾¾¾

Max.3232201540773¾103488°

Rev.1.0013August16,2005

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HT82V26A

28-pinSOP(300mil)OutlineDimensions

SymbolABCC¢DEFGHa

Dimensionsinmil

Min.3942901469792¾43240°

Nom.¾¾¾¾¾50¾¾¾¾

Max.41930020713104¾¾381210°

Rev.1.0014August16,2005

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HT82V26A

ProductTapeandReelSpecifications

ReelDimensions

SOP28W(300mil)

SymbolABCDT1T2

Description

ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth

SpaceBetweenFlangeReelThickness

Dimensionsinmm

330±1.062±1.513.0+0.5

-0.22.0±0.524.8+0.3

-0.230.2±0.2

Rev.1.0015August16,2005

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HT82V26A

CarrierTapeDimensions

SOP28W(300mil)

SymbolWPEFDD1P0P1A0B0K0tC

Description

CarrierTapeWidthCavityPitchPerforationPosition

CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch

CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth

CarrierTapeThicknessCoverTapeWidth

Dimensionsinmm

24.0±0.312.0±0.11.75±0.111.5±0.11.5+0.11.5+0.254.0±0.12.0±0.110.85±0.118.34±0.12.97±0.10.35±0.0121.3

Rev.1.0016August16,2005

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HT82V26A

HoltekSemiconductorInc.(Headquarters)

No.3,CreationRd.II,SciencePark,Hsinchu,TaiwanTel:886-3-563-1999Fax:886-3-563-11http://www.holtek.com.tw

HoltekSemiconductorInc.(TaipeiSalesOffice)

4F-2,No.3-2,YuanQuSt.,NankangSoftwarePark,Taipei115,TaiwanTel:886-2-2655-7070Fax:886-2-2655-7373

Fax:886-2-2655-7383(Internationalsaleshotline)

HoltekSemiconductorInc.(ShanghaiSalesOffice)

7thFloor,Building2,No.8,YiShanRd.,Shanghai,China200233Tel:021-85-5560Fax:021-85-0313

http://www.holtek.com.cn

HoltekSemiconductorInc.(ShenzhenSalesOffice)

5/F,UnitA,ProductivityBuilding,CrossofScienceM3rdRoadandGaoxinM2ndRoad,SciencePark,NanshanDistrict,Shenzhen,China518057

Tel:0755-8616-9908,8616-9308Fax:0755-8616-9533

HoltekSemiconductorInc.(BeijingSalesOffice)

Suite1721,JinyuTower,A129WestXuanWuMenStreet,XichengDistrict,Beijing,China100031Tel:010-61-0030,61-7751,61-7752Fax:010-61-0125

HoltekSemiconductorInc.(ChengduSalesOffice)

709,Building3,ChampagnePlaza,No.97DongdaStreet,Chengdu,Sichuan,China610016Tel:028-6653-6590Fax:028-6653-6591

HolmateSemiconductor,Inc.(NorthAmericaSalesOffice)46729FremontBlvd.,Fremont,CA94538Tel:510-252-9880Fax:510-252-9885

http://www.holmate.com

CopyrightÓ2005byHOLTEKSEMICONDUCTORINC.

TheinformationappearinginthisDataSheetisbelievedtobeaccurateatthetimeofpublication.However,Holtekas-sumesnoresponsibilityarisingfromtheuseofthespecificationsdescribed.TheapplicationsmentionedhereinareusedsolelyforthepurposeofillustrationandHoltekmakesnowarrantyorrepresentationthatsuchapplicationswillbesuitablewithoutfurthermodification,norrecommendstheuseofitsproductsforapplicationthatmaypresentarisktohumanlifeduetomalfunctionorotherwise.Holtek¢sproductsarenotauthorizedforuseascriticalcomponentsinlifesupportdevicesorsystems.Holtekreservestherighttoalteritsproductswithoutpriornotification.Forthemostup-to-dateinformation,pleasevisitourwebsiteathttp://www.holtek.com.tw.

Rev.1.0017August16,2005