HT82K95E/HT82K95A
USBMultimediaKeyboardEncoder8-BitMCU
TechnicalDocument
·ToolsInformation·FAQs·ApplicationNoteFeatures
·Operatingvoltage:
·4096´15programmemoryROM·160´8datamemoryRAM
·AllI/Oportssupportwake-upoptions
·HALTfunctionandwake-upfeaturereducepower
fSYS=6M/12MHz:4.2V~5.5V
·Lowvoltageresetfunction·32bidirectionalI/Olines(max.)
·8-bitprogrammabletimer/eventcounterwithover-
flowinterrupt
·16-bitprogrammabletimer/eventcounterandover-
consumption
·8-levelsubroutinenesting
·Upto0.33msinstructioncyclewith12MHzsystem
flowinterrupts
·Crystaloscillator(6MHzor12MHz)
·WatchdogTimer
·PS2andUSBmodessupported·USB1.1lowspeedfunction
·3endpointssupported(endpoint0included)
clockatVDD=5V
·Bitmanipulationinstruction·15-bittablereadinstruction·63powerfulinstructions
·Allinstructionsinoneortwomachinecycles·20/28-pinSOP,20/48-pinSSOPpackage
GeneralDescription
Thisdeviceisan8-bithighperformanceRISCarchitec-turemicrocontrollerdesignedforUSBproductapplica-tions.Itisparticularlysuitableforuseinproductssuchaskeyboards.AHALTfeatureisincludedtoreduce
powerconsumption.ThemaskversionHT82K95AisfullypinandfunctionallycompatiblewiththeOTPver-sionHT82K95Edevice.
Rev.1.201October24,2005
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HT82K95E/HT82K95ABlockDiagram
Rev.1.202October24,2005
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HT82K95E/HT82K95APinAssignment
PinDescription
PinName
I/O
ROMCodeOption
Description
PA0~PA5PA6/TMR0PA7/TMR1
Bidirectional8-bitinput/outputport.Eachbitcanbeconfiguredasawake-upinputbyROMcodeoption.Theinputoroutputmodeiscon-trolledbyPAC(PAcontrolregister).Pull-high
Pull-highresistoroptions:PA0~PA7I/OWake-up
CMOS/NMOS/PMOSCMOS/NMOS/PMOSoptions:PA0~PA7
Wakeupoptions:PA0~PA7
PA6andPA7arepin-sharedwithTMR0andTMR1input,respectively.
Pull-highWake-up
Bidirectional8-bitinput/outputport.SoftwareinstructionsdeterminetheCMOSoutputorSchmitttriggerinputwithpull-highresistor(determinedbypull-highoptions).
Wake-upoptions:PB0~PB7
BidirectionalI/Olines.SoftwareinstructionsdeterminetheCMOSout-putorSchmitttriggerinputwithpull-highresistor(determinedbypull-highoptions).
Wake-upoptions:PD0~PD7Negativepowersupply,ground
BidirectionalI/Olines.SoftwareinstructionsdeterminetheCMOSout-putorSchmitttriggerinputwithpull-highresistor(determinedbypull-highoptions).
Wake-upoptions:PC0~PC7Schmitttriggerresetinput.ActivelowPositivepowersupply3.3Vregulatoroutput
PB0~PB7I/O
PD0~PD7I/O
Pull-highWake-up
¾Pull-highWake-up
¾¾¾
VSS¾
PC0~PC7I/O
RESVDDV33O
I¾O
Rev.1.203October24,2005
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HT82K95E/HT82K95APinNameUSBD+/CLKUSBD-/DATAOSC1OSC2
I/OI/OI/OIO
ROMCodeOption
¾¾¾
Description
USBD+orPS2CLKI/Oline
USBorPS2functioniscontrolledbysoftwarecontrolregisterUSBD-orPS2DATAI/Oline
USBorPS2functioniscontrolledbysoftwarecontrolregisterOSC1,OSC2areconnectedtoa6MHzor12MHzCrystal/resonator(determinedbysoftwareinstructions)fortheinternalsystemclock.
AbsoluteMaximumRatings
SupplyVoltage...........................VSS-0.3VtoVSS+6.0VInputVoltage..............................VSS-0.3VtoVDD+0.3V
StorageTemperature............................-50°Cto125°COperatingTemperature...............................0°Cto70°C
Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder²AbsoluteMaximumRatings²may
causesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliabil-ity.
D.C.Characteristics
Symbol
Parameter
TestConditionsVDD¾5V5V5V5V5V5V5V5V
VOL=3.4VVOL=0.4VVOL=0.4VVOH=3.4VVOH=3.4V
¾¾
IV33O=-5mA
ConditionsfSYS=6MHzfSYS=12MHzNoload,fSYS=6MHzNoload,fSYS=12MHzNoload,systemHALT,USBsuspend
Noload,systemHALT,USBsuspend
¾¾¾¾
Min.4.24.2¾¾¾¾0200.9VDD1027-2-122533.0
Typ.¾¾6.57.5¾¾¾¾¾¾15410-4-18503.43.3
Max.5.55.512162502300.850.4VDDVDD20813-8-24804.03.6
Ta=25°CUnitVVmAmAmAmAVVVVmAmAmAmAmAkWVV
VDDIDD1IDD2ISTB1ISTB2VIL1VIH1VIL2VIH2IOL1IOL2IOL3IOH1IOH2RPHVLVRVV33O
OperatingVoltage
OperatingCurrent(6MHzCrystal)OperatingCurrent(12MHzCrystal)StandbyCurrent(WDTEnabled)StandbyCurrent(WDTDisabled)InputLowVoltageforI/OPortsInputHighVoltageforI/OPortsInputLowVoltage(RES)InputHighVoltage(RES)I/OPortSinkCurrentforPA1~PA7,PB,PC,
5V
PD
I/OPortSinkCurrentforPA1~PA7,PB,PC,
5V
PD
I/OPortSinkCurrentforPA0
5V
I/OPortSourceCurrentforPA1~PA7,PB,
5V
PC,PD
I/OPortSourceCurrentforPA0Pull-highResistanceforPA,PB,PC,PDLowVoltageReset3.3VRegulatorOutput
5V5V¾5V
Rev.1.204October24,2005
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HT82K95E/HT82K95AA.C.Characteristics
SymbolfSYSfTIMER
Parameter
SystemClock(CrystalOSC)TimerI/PFrequency(TMR)
TestConditionsVDD5V5V5V5V¾¾
Conditions
¾¾¾
WithoutWDTprescalerWithoutWDTprescaler
¾
Wake-upfromHALT
tSSTtINT
SystemStart-upTimerPeriod
¾
Power-up,WatchdogTime-outfromnormal
¾
Min.60154¾1¾¾1
Typ.Max.¾¾3181024¾10241024¾
12127016¾¾¾¾¾
Ta=25°CUnitMHzMHzmsmstSYSmstSYStWDTOSC
ms
tWDTOSCWatchdogOscillatortWDT1tWDT2tRES
WatchdogTime-outPeriod(WDTOSC)WatchdogTime-outPeriod(SystemClock)ExternalResetLowPulseWidth
InterruptPulseWidth¾
Rev.1.205October24,2005
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HT82K95E/HT82K95AFunctionalDescription
ExecutionFlow
Thesystemclockforthemicrocontrollerisderivedfromacrystal.Thesystemclockisinternallydividedintofournon-overlappingclocks.Oneinstructioncycleconsistsoffoursystemclockcycles.
Instructionfetchingandexecutionarepipelinedinsuchawaythatafetchtakesaninstructioncyclewhilede-codingandexecutiontakesthenextinstructioncycle.However,thepipeliningschemeallowseachinstructiontobeeffectivelyexecutedinacycle.Ifaninstructionchangestheprogramcounter,twocyclesarerequiredtocompletetheinstruction.ProgramCounter-PC
Theprogramcounter(PC)controlsthesequenceinwhichtheinstructionsstoredintheprogramROMareexecutedanditscontentsspecifyafullrangeofpro-grammemory.
Afteraccessingaprogrammemorywordtofetchanin-structioncode,thecontentsoftheprogramcounterare
incrementedbyone.Theprogramcounterthenpointstothememorywordcontainingthenextinstructioncode.Whenexecutingajumpinstruction,conditionalskipex-ecution,loadingPCLregister,subroutinecallorreturnfromsubroutine,initialreset,internalinterrupt,externalinterruptorreturnfrominterrupts,thePCmanipulatestheprogramtransferbyloadingtheaddresscorre-spondingtoeachinstruction.
Theconditionalskipisactivatedbyinstructions.Oncetheconditionismet,thenextinstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycyclereplacesittogettheproperinstruction.Otherwiseproceedtothenextinstruction.
Thelowerbyteoftheprogramcounter(PCL)isaread-ableandwriteableregister(06H).MovingdataintothePCLperformsashortjump.ThedestinationwillbewithinthecurrentprogramROMpage.
Whenacontroltransfertakesplace,anadditionaldummycycleisrequired.
ExecutionFlow
Mode
InitialresetUSBinterrupt
Timer/EventCounter0overflowTimer/EventCounter1overflowSkipLoadingPCLJump,callbranchReturnfromsubroutine
ProgramCounter
*110000
*100000
*90000
*80000
*70000
*60000
*50000
*40000
*30011
*20101
*10000
*00000
ProgramCounter+2
*11#11S11
*10#10S10
*9#9S9
*8#8S8
@7#7S7
@6#6S6
@5#5S5
@4#4S4
@3#3S3
@2#2S2
@1#1S1
@0#0S0
ProgramCounter
Note:*11~*0:Programcounterbits
#11~#0:Instructioncodebits
S11~S0:Stackregisterbits@7~@0:PCLbits
Rev.1.206October24,2005
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HT82K95E/HT82K95AProgramMemory-ROM
Theprogrammemoryisusedtostoretheprogramin-structionswhicharetobeexecuted.Italsocontainsdata,table,andinterruptentries,andisorganizedinto4096´15bits,addressedbytheprogramcounterandta-blepointer.
Certainlocationsintheprogrammemoryarereservedforspecialusage:
·Location000H
·Location00CH
ThislocationisreservedfortheTimer/EventCounter1interruptserviceprogram.IfatimerinterruptresultsfromaTimer/EventCounter1overflow,andtheinter-ruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation00CH.
·Tablelocation
Thisareaisreservedforprograminitialization.Afterchipreset,theprogramalwaysbeginsexecutionatlo-cation000H.
·Location004H
Anylocationintheprogrammemorycanbeusedaslook-uptables.TherearethreemethodtoreadtheROMdatabytwotablereadinstructions:²TABRDC²and²TABRDL²,transferthecontentsofthelower-orderbytetothespecifieddatamemory,andthehigher-orderbytetoTBLH(08H).Thethreemethodsareshownasfollows:
¨
ThisareaisreservedfortheUSBinterruptserviceprogram.IftheUSBinterruptisactivated,theinterruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation004H.
·Location008H
Theinstructions²TABRDC[m]²(thecurrentpage,onepage=256words),wherethetablelocationsisdefinedbyTBLP(07H)inthecurrentpage.AndtheROMcodeoptionTBHPisdisabled(default).Theinstructions²TABRDC[m]²,wherethetablelo-cationsisdefinedbyregistersTBLP(07H)andTBHP(01FH).AndtheROMcodeoptionTBHPisenabled.
Theinstructions²TABRDL[m]²,wherethetablelo-cationsisdefinedbyRegistersTBLP(07H)inthelastpage(0F00H~0FFFH).
¨
ThisareaisreservedfortheTimer/EventCounter0in-terruptserviceprogram.IfatimerinterruptresultsfromaTimer/EventCounter0overflow,andifthein-terruptisenabledandthestackisnotfull,theprogrambeginsexecutionatlocation008H.
¨
ProgramMemory
Onlythedestinationofthelower-orderbyteintheta-bleiswell-defined,theotherbitsofthetablewordaretransferredtothelowerportionofTBLH,andthere-maining1-bitwordsarereadas²0².TheTableHigher-orderbyteregister(TBLH)isreadonly.Theta-blepointer(TBLP,TBHP)isaread/writeregister(07H,1FH),whichindicatesthetablelocation.Beforeac-cessingthetable,thelocationmustbeplacedintheTBLPandTBHP(IftheOTPoptionTBHPisdisabled,thevalueinTBHPhasnoeffect).TheTBLHisreadonlyandcannotberestored.IfthemainroutineandtheISR(InterruptServiceRoutine)bothemploythetablereadinstruction,thecontentsoftheTBLHinthemainroutinearelikelytobechangedbythetablereadinstructionusedintheISR.Errorscanoccur.Inotherwords,usingthetablereadinstructioninthemainrou-tineandtheISRsimultaneouslyshouldbeavoided.However,ifthetablereadinstructionhastobeappliedinboththemainroutineandtheISR,theinterruptshouldbedisabledpriortothetablereadinstruction.TableLocation
InstructionTABRDC[m]TABRDL[m]
*11P111
*10P101
*9P91
*8P81
*7@7@7
*6@6@6
*5@5@5
*4@4@4
*3@3@3
*2@2@2
*1@1@1
*0@0@0
TableLocation
Note:*11~*0:Tablelocationbits
@7~@0:Tablepointerbits
P11~P8:CurrentprogramcounterbitswhenTBHPisdisabled
TBHPregisterbit3~bit0whenTBHPisenabled
Rev.1.207October24,2005
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HT82K95E/HT82K95AItwillnotbeenableduntiltheTBLHhasbeenbackedup.Alltablerelatedinstructionsrequiretwocyclestocompletetheoperation.Theseareasmayfunctionasnormalprogrammemorydependingontherequire-ments.
OnceTBHPisenabled,theinstruction²TABRDC[m]²readstheROMdataasdefinedbyTBLPandTBHPvalue.Otherwise,theROMcodeoptionTBHPisdis-abled,theinstruction²TABRDC[m]²readstheROMdataasdefinedbyTBLPandthecurrentprogramcounterbits.
StackRegister-STACK
Thisisaspecialpartofthememorywhichisusedtosavethecontentsoftheprogramcounteronly.Thestackisorganizedinto8levelsandisneitherpartofthedatanorpartoftheprogramspace,andisneitherread-ablenorwriteable.Theactivatedlevelisindexedbythestackpointer(SP)andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheprogramcounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction(RETorRETI),thepro-gramcounterisrestoredtoitspreviousvaluefromthestack.Afterachipreset,theSPwillpointtothetopofthestack.
Ifthestackisfullandanon-maskedinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.Whenthestackpointerisdecremented(byRETorRETI),theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowal-lowingtheprogrammertousethestructuremoreeasily.Inasimilarcase,ifthestackisfullanda²CALL²issub-sequentlyexecuted,stackoverflowoccursandthefirstentrywillbelost(onlythemostrecent8returnad-dressesarestored).
DataMemory-RAMforBank0
Thedatamemoryisdesignedwith190´8bits.Thedatamemoryisdividedintotwofunctionalgroups:spe-cialfunctionregistersandgeneralpurposedatamem-ory(160´8).Mostareread/write,butsomearereadonly.
Thespecialfunctionregistersincludetheindirectad-dressingregisters(R0;00H,R1;02H),Bankregister(BP,04H),Timer/EventCounter0(TMR0;0DH),Timer/EventCounter0controlregister(TMR0C;0EH),Timer/EventCounter1higherorderbyteregister(TMR1H;0FH),Timer/EventCounter1lowerorderbyteregister(TMR1L;10H),Timer/EventCounter1controlregister(TMR1C;11H),programcounterlower-orderbyteregister(PCL;06H),memorypointerregisters(MP0;01H,MP1;03H),accumulator(ACC;05H),tablepointer(TBLP;07H,TBHP;1FH),tablehigher-orderbyteregister(TBLH;08H),statusregister(STATUS;0AH),interruptcontrolregister(INTC;0BH),Rev.1.20
8
Bank0RAMMapping
WatchdogTimeroptionsettingregister(WDTS;09H),I/Oregisters(PA;12H,PB;14H,PC;16H,PD;18H),I/Ocontrolregisters(PAC;13H,PBC;15H,PCC;17H,PDC;19H).USB/PS2statusandcontrolregister(USC;1AH),USBendpointinterruptstatusregister(USR;1BH),systemclockcontrolregister(SCC;1CH).Theremainingspacebeforethe20Hisreservedforfu-tureexpansionusageandreadingtheselocationswillget²00H².Thegeneralpurposedatamemory,ad-dressedfrom20HtoBFH,isusedfordataandcontrolinformationunderinstructioncommands.
Allofthedatamemoryareascanhandlearithmetic,logic,increment,decrementandrotateoperationsdi-rectly.Exceptforsomededicatedbits,eachbitinthedatamemorycanbesetandresetby²SET[m].i²and²CLR[m].i².Theyarealsoindirectlyaccessiblethroughmemorypointerregisters(MP0orMP1).
October24,2005
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HT82K95E/HT82K95ADataMemory-RAMforBank1
ThespecialfunctionregistersusedinUSBinterfacearelocatedinRAMbank1.InordertoaccesstheBank1register,onlytheIndirectaddressingpointerMP1canbeusedandtheBankregisterBPshouldbesetto²1².ThemappingofRAMbank1isasshown.IndirectAddressingRegister
Location00Hand02Hareindirectaddressingregistersthatarenotphysicallyimplemented.Anyread/writeop-erationof[00H]([02H])willaccessdatamemorypointedtobyMP0(MP1).Readinglocation00H(02H)itselfindi-rectlywillreturntheresult00H.Writingindirectlyresultsinnooperation.
Theindirectaddressingpointer(MP0)alwayspointtoBank0RAMaddressesregardlessofthevalueoftheBankRegister(BP).
Theindirectaddressingpointer(MP1)canaccessBank0orBank1RAMdataaccordingtothevalueofBPwhichissetto²0²or²1²respectively.
Thememorypointerregisters(MP0andMP1)are8-bitregisters.
Accumulator
TheaccumulatoriscloselyrelatedtoALUoperations.Itisalsomappedtolocation05Hofthedatamemoryandcancarryoutimmediatedataoperations.Thedatamovementbetweentwodatamemorylocationsmustpassthroughtheaccumulator.ArithmeticandLogicUnit-ALU
Thiscircuitperforms8-bitarithmeticandlogicopera-tions.TheALUprovidesthefollowingfunctions:
·Arithmeticoperations(ADD,ADC,SUB,SBC,DAA)·Logicoperations(AND,OR,XOR,CPL)·Rotation(RL,RR,RLC,RRC)·IncrementandDecrement(INC,DEC)·Branchdecision(SZ,SNZ,SIZ,SDZ)
TheALUnotonlysavestheresultsofadataoperationbutalsochangesthestatusregister.StatusRegister-STATUS
This8-bitregister(0AH)containsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Italsorecordsthestatusinformationandcontrolstheoperationsequence.
WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddi-tionoperationsrelatedtothestatusregistermaygivedifferentresultsfromthoseintended.
TheTOflagcanbeaffectedonlybysystempower-up,aWDTtime-outorexecutingthe²CLRWDT²or²HALT²instruction.ThePDFflagcanbeaffectedonlybyex-ecutingthe²HALT²or²CLRWDT²instructionordur-ingasystempower-up.
TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.Function
Bank1RAMMapping
BitNo.0
LabelC
Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.
ACissetifanoperationresultsinacarryoutofthelownibblesinadditionornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
Zissetiftheresultofanarithmeticorlogicoperationiszero;otherwiseZiscleared.OVissetiftheoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.
PDFisclearedbysystempower-uporexecutingthe²CLRWDT²instruction.PDFissetbyexecutingthe²HALT²instruction.
TOisclearedbysystempower-uporexecutingthe²CLRWDT²or²HALT²instruction.TOissetbyaWDTtime-out.Unusedbit,readas²0²
Status(0AH)Register
123456~7
ACZOVPDFTO¾
Rev.1.209October24,2005
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HT82K95E/HT82K95AInaddition,onenteringtheinterruptsequenceorexe-cutingthesubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusareimportantandifthesubroutinecancor-ruptthestatusregister,precautionsmustbetakentosaveitproperly.Interrupt
Thedeviceprovidesanexternalinterruptandinternaltimer/eventcounterinterrupts.TheInterruptControlRegister(INTC;0BH)containstheinterruptcontrolbitstosettheenable/disableandtheinterruptrequestflags.Onceaninterruptsubroutineisserviced,alltheotherin-terruptswillbeblocked(byclearingtheEMIbit).Thisschememaypreventanyfurtherinterruptnesting.Otherinterruptrequestsmayoccurduringthisintervalbutonlytheinterruptrequestflagisrecorded.Ifacertaininter-ruptrequiresservicingwithintheserviceroutine,theEMIbitandthecorrespondingbitoftheINTCmaybesettoallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedin-terruptisenabled,untiltheSPisdecremented.Ifimmedi-ateserviceisdesired,thestackmustbepreventedfrombecomingfull.
Allthesekindsofinterruptshaveawake-upcapability.Asaninterruptisserviced,acontroltransferoccursbypushingtheprogramcounterontothestack,followedbyabranchtoasubroutineatspecifiedlocationinthepro-grammemory.Onlytheprogramcounterispushedontothestack.Ifthecontentsoftheregisterorstatusregister(STATUS)arealteredbytheinterruptserviceprogramwhichcorruptsthedesiredcontrolsequence,thecon-tentsshouldbesavedinadvance.
USBinterruptsaretriggeredbythefollowingUSBeventsandtherelatedinterruptrequestflag(USBF;bit4oftheINTC)willbeset.
·ThecorrespondingUSBFIFOisaccessedfromthe
Whentheinterruptisenabled,thestackisnotfullandtheexternalinterruptisactive,asubroutinecalltoloca-tion04Hwilloccur.Theinterruptrequestflag(USBF)andEMIbitswillbeclearedtodisableotherinterrupts.WhenthePCHostaccesstheFIFOoftheHT82K95E/HT82K95A,thecorrespondingrequestbitoftheUSRisset,andaUSBinterruptistriggered.SousercaneasilydecidewhichFIFOisaccessed.Whentheinterrupthasbeenserved,thecorrespondingbitshouldbeclearedbyfirmware.WhentheHT82K95E/HT82K95AreceivesaUSBSuspendsignalfromtheHostPC,thesuspendline(bit0oftheUSC)oftheHT82K95E/HT82K95AissetandaUSBinterruptisalsotriggered.
AlsowhentheHT82K95E/HT82K95AreceivesaRe-sumesignalfromtheHostPC,theresumeline(bit3oftheUSC)ofHT82K95E/HT82K95AissetandaUSBin-terruptistriggered.
WheneveraUSBresetsignalisdetected,theUSBin-terruptistriggered.
TheinternalTimer/EventCounter0interruptisinitial-izedbysettingtheTimer/EventCounter0interruptre-questflag(;bit5ofINTC),causedbyatimer0overflow.Whentheinterruptisenabled,thestackisnotfullandtheT0Fbitisset,asubroutinecalltolocation08Hwilloccur.Therelatedinterruptrequestflag(T0F)willbere-setandtheEMIbitclearedtodisablefurtherinterrupts.TheinternalTimer/EvenCounter1interruptisinitializedbysettingtheTimer/EventCounter1interruptrequestflag(;bit6ofINTC),causedbyatimer1overflow.Whentheinterruptisenabled,thestackisnotfullandtheT1Fisset,asubroutinecalltolocation0CHwilloccur.Therelatedinterruptrequestflag(T1F)willberesetandtheEMIbitclearedtodisablefurtherinterrupts.
Duringtheexecutionofaninterruptsubroutine,otherin-terruptacknowledgesignalsarehelduntilthe²RETI²in-structionisexecutedortheEMIbitandtherelatedinterruptcontrolbitaresetto²1²(ifthestackisnotfull).Toreturnfromtheinterruptsubroutine,²RET²or²RETI²maybeinvoked.RETIwillsettheEMIbittoenableanin-terruptservice,butRETwillnot.Function
PC
·TheUSBsuspendssignalfromthePC·TheUSBresumessignalfromthePC·TheUSBsendsResetsignal
BitNo.01234567
LabelEMIEUIET0IET1IUSBFT0FT1F¾
Controlsthemaster(global)interrupt(1=enabled;0=disabled)ControlstheUSBinterrupt(1=enabled;0=disabled)
ControlstheTimer/EventCounter0interrupt(1=enabled;0=disabled)ControlstheTimer/EventCounter1interrupt(1=enabled;0=disabled)USBinterruptrequestflag(1=active;0=inactive)
InternalTimer/EventCounter0requestflag(1=active;0=inactive)InternalTimer/EventCounter1requestflag(1=active;0=inactive)Unusedbit,readas²0²
INTC(0BH)Register
Rev.1.2010October24,2005
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HT82K95E/HT82K95AInterrupts,occurringintheintervalbetweentherisingedgesoftwoconsecutiveT2pulses,willbeservicedonthelatterofthetwoT2pulses,ifthecorrespondinginter-ruptsareenabled.Inthecaseofsimultaneousrequeststhefollowingtableshowstheprioritythatisapplied.ThesecanbemaskedbyresettingtheEMIbit.No.abc
InterruptSource
USBinterrupt
Timer/EventCounter0overflowTimer/EventCounter1overflow
PriorityVector123
04H08H0CH
AcrystalacrossOSC1andOSC2isneededtoprovidethefeedbackandphaseshiftrequiredfortheoscillator.Nootherexternalcomponentsarerequired.Insteadofacrystal,aresonatorcanalsobeconnectedbetweenOSC1andOSC2togetafrequencyreference,buttwoexternalcapacitorsinOSC1andOSC2arerequired.TheWDToscillatorisafreerunningon-chipRCoscilla-tor,andnoexternalcomponentsarerequired.Evenifthesystementersthepowerdownmode,thesystemclockisstopped,buttheWDToscillatorstillworkswithinaperiodofapproximately31ms.TheWDToscillatorcanbedisabledbyROMcodeoptiontoconservepower.WatchdogTimer-WDT
TheWDTclocksourceisimplementedbyadedicatedRCoscillator(WDToscillator),orinstructionclock(sys-temclockdividedby4),determinestheROMcodeop-tion.Thistimerisdesignedtopreventasoftwaremalfunctionorsequencefromjumpingtoanunknownlocationwithunpredictableresults.TheWatchdogTimercanbedisabledbyROMcodeoption.IftheWatchdogTimerisdisabled,alltheexecutionsrelatedtotheWDTresultinnooperation.
OncetheinternalWDToscillator(RCoscillator,nor-mallywithaperiodof31ms/5V)isselected,itisfirstdi-videdby256(8-stage)togetthenominaltime-outperiodof8ms/5V.Thistime-outperiodmayvarywithtemperatures,VDDandprocessvariations.ByinvokingtheWDTprescaler,longertime-outperiodscanbereal-ized.WritingdatatoWS2,WS1,WS0(bits2,1,0oftheWDTS)cangivedifferenttime-outperiods.IfWS2,WS1,andWS0areallequalto1,thedivisionratioisupto1:128,andthemaximumtime-outperiodis1s/5V.IftheWDToscillatorisdisabled,theWDTclockmaystillcomefromtheinstructionclockandoperatesinthesamemannerexceptthatintheHALTstatetheWDTmaystopcountingandloseitsprotectingpurpose.Inthissituationthelogiccanonlyberestartedbyexternallogic.Thehighnibbleandbit3oftheWDTSarere-servedforuser¢sdefinedflags,whichcanonlybesetto²10000²(WDTS.7~WDTS.3).
Ifthedeviceoperatesinanoisyenvironment,usingtheon-chip32kHzRCoscillator(WDTOSC)isstronglyrec-ommended,sincetheHALTwillstopthesystemclock.
TheTimer/EventCounter0/1interruptrequestflag(T0F/T1F),USBinterruptrequestflag(USBF),enableTimer/EventCounter0/1interruptbit(ET0I/ET1I),en-ableUSBinterruptbit(EUI)andenablemasterinterruptbit(EMI)constituteaninterruptcontrolregister(INTC)whichislocatedat0BHinthedatamemory.EMI,EUI,ETIareusedtocontroltheenabling/disablingofinter-rupts.Thesebitspreventtherequestedinterruptfrombeingserviced.Oncetheinterruptrequestflags(TF,USBF)areset,theywillremainintheINTCregisteruntiltheinterruptsareservicedorclearedbyasoftwarein-struction.
Itisrecommendedthataprogramdoesnotusethe²CALLsubroutine²withintheinterruptsubroutine.In-terruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediatelyinsomeapplications.Ifonlyonestackisleftandenablingtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedam-agedoncethe²CALL²operatesintheinterruptsubrou-tine.
OscillatorConfiguration
Thereisanoscillatorcircuitsinthemicrocontroller.
SystemOscillator
Thisoscillatorisdesignedforsystemclocks.TheHALTmodestopsthesystemoscillatorandignoresanexter-nalsignaltoconservepower.
WatchdogTimer
Rev.1.20
11
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HT82K95E/HT82K95AWS200001111
WS100110011
WS001010101
DivisionRatio
1:11:21:41:81:161:321:1:128
cutingthe²HALT²instruction.TheTOflagissetiftheWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandSP,theothersremainintheiroriginalstatus.
TheI/Oportswake-upandinterruptmethodscanbeconsideredasacontinuationofnormalexecution.EachbitinthePortAcanbeindependentlyselectedtowakeupthedevicebyoption.PB,PCandPDcanalsobese-lectedtowakeupthedevicebyoption.UponawakeningfromanI/Oportstimulus,theprogramwillresumeexe-cutionofthenextinstruction.Ifitawakensfromaninter-rupt,twosequencemayoccur.Iftherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,theprogramwillresumeexecutionatthenextinstruc-tion.Iftheinterruptisenabledandthestackisnotfull,theregularinterruptresponsetakesplace.Ifaninterruptrequestflagissetto²1²beforeenteringtheHALTmode,thewake-upfunctionoftherelatedinterruptwillbedis-abled.Onceawake-upeventoccurs,ittakes1024tSYS(systemclockperiod)toresumenormaloperation.Inotherwords,adummyperiodwillbeinsertedafterawake-up.Ifthewake-upresultsfromaninterruptac-knowledgesignal,theactualinterruptsubroutineexecu-tionwillbedelayedbyoneormorecycles.Ifthewakeupresultsinthenextinstructionexecution,thiswillbeexe-cutedimmediatelyafterthedummyperiodiscompleted.Tominimizepowerconsumption,alltheI/OpinsshouldbecarefullymanagedbeforeenteringtheHALTstatus.Reset
Therearethreewaysinwhicharesetcanoccur:
·RESresetduringnormaloperation·RESresetduringHALT
·WDTtime-outresetduringnormaloperation
WDTS(09H)Register
TheWDToverflowundernormaloperationwillinitializea²chipreset²andsetthestatusbit²TO².ButintheHALTmode,theoverflowwillinitializea²warmreset²andonlytheProgramCounterandSPareresettozero.ToclearthecontentsoftheWDT(includingtheWDTprescaler),threemethodsareemployed;externalreset(alowleveltoRES),softwareinstructionanda²HALT²instruction.Thesoftwareinstructioninclude²CLRWDT²andtheotherset-²CLRWDT1²and²CLRWDT2².Ofthesetwotypesofinstruction,onlyonecanbeactivedependingontheROMcodeoption-²CLRWDTtimesselectionoption².Ifthe²CLRWDT²isse-lected(i.e.CLRWDTtimesequalone),anyexecutionofthe²CLRWDT²instructionwillcleartheWDT.Inthecasewherein²CLRWDT1²and²CLRWDT2²arecho-sen(i.e.CLRWDTtimesisequaltotwo),thesetwoin-structionsmustbeexecutedtocleartheWDT,otherwise,theWDTmayresetthechipasaresultoftime-out.
PowerDownOperation-HALT
TheHALTmodeisinitializedbythe²HALT²instructionandresultsinthefollowing:
·ThesystemoscillatorwillbeturnedoffbuttheWDT
oscillatorremainsrunning(iftheWDToscillatorisse-lected).
·Thecontentsoftheon-chipRAMandregistersremainunchanged.
·WDTandWDTprescalerwillbeclearedandre-
countedagain(iftheWDTclockisfromtheWDTos-cillator).
·AlloftheI/Oportsmaintaintheiroriginalstatus.·ThePDFflagissetandtheTOflagiscleared.
TheWDTtime-outduringHALTisdifferentfromotherchipresetconditions,sinceitcanperforma²warmre-set²thatresetsonlytheProgramCounterandSP,leav-ingtheothercircuitsintheiroriginalstate.Someregis-tersremainunchangedduringotherresetconditions.Mostregistersareresettothe²initialcondition²whentheresetconditionsaremet.ByexaminingthePDFandTOflags,theprogramcandistinguishbetweendifferent²chipresets².TOPDF0u011
0u1u1
RESETConditions
RESresetduringpower-upRESresetduringnormaloperationRESwake-upHALT
WDTtime-outduringnormaloperationWDTwake-upHALT
ThesystemcanleavetheHALTmodebymeansofanexternalreset,aninterrupt,anexternalfallingedgesig-nalonI/OportsoraWDToverflow.AnexternalresetcausesadeviceinitializationandtheWDToverflowper-formsa²warmreset².AftertheTOandPDFflagsareexamined,thecauseforchipresetcanbedetermined.ThePDFflagisclearedbyasystempower-uporexe-cutingthe²CLRWDT²instructionandissetwhenexe-
Note:²u²standsfor²unchanged²
Toguaranteethatthesystemoscillatorisstartedandstabilized,theSST(SystemStart-upTimer)providesan
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HT82K95E/HT82K95Aextradelayof1024systemclockpulseswhenthesys-temresets(power-up,WDTtime-outorRESreset)orwhenthesystemawakesfromtheHALTstate.Whenasystemresetoccurs,anSSTdelayisaddedduringtheresetperiod.AnywakeupfromHALTwillen-abletheSSTdelay.
ResetConfiguration
ResetTimingChart
Thefunctionalunitchipresetstatusareshownbelow.ProgramCounterInterruptPrescaler
000HDisableClear
Clear.Aftermasterreset,WDTbeginscountingInputmode
Pointstothetopofthestack
WDT
Timer/eventCounterOffInput/outputPorts
ResetCircuit
StackPointer
Thestatusoftheregistersaresummarizedinthefollowingtable.RegisterTMR0TMR0CTMR1HTMR1LTMR1CProgramCounterMP0MP1ACCTBLPTBLHSTATUSINTCWDTSPAPACPBPBCPCPCCPD
Reset(PowerOn)xxxxxxxx00-01000xxxxxxxxxxxxxxxx00-01---000Hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxx--00xxxx-00000001000011111111111111111111111111111111111111111111111111111111111
WDTTime-out(NormalOperation)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--1uuuuu-00000001000011111111111111111111111111111111111111111111111111111111111
RESReset(NormalOperation)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--uuuuuu-00000001000011111111111111111111111111111111111111111111111111111111111
RESReset(HALT)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--01uuuu-00000001000011111111111111111111111111111111111111111111111111111111111
WDTTime-Out(HALT)*uuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuuu-uu---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--11uuuu-uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu
USB-Reset(Normal)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--uuuuuu-00000001000011111111111111111111111111111111111111111111111111111111111
USB-Reset(HALT)uuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---000Huuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuu--01uuuu-00000001000011111111111111111111111111111111111111111111111111111111111
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HT82K95E/HT82K95ARegisterPDCPIPE_CTRLAWRPIPESTALLSIESMISCEndpt_ENFIFO0FIFO1FIFO2USCUSRSCCNote:
Reset(PowerOn)1111111100000111000000000000000000000111000000000000000000000111xxxxxxxxxxxxxxxxxxxxxxxx11xx00000100000000000000
WDTTime-out(NormalOperation)11111111uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuxxuuuuuuuuuuuuuuuuuuuu
RESReset(NormalOperation)1111111100000111000000000000000000000111000000000000000000000111uuuuuuuuuuuuuuuuuuuuuuuu11xx00000100000000000000
RESReset(HALT)1111111100000111000000000000000000000111000000000000000000000111uuuuuuuuuuuuuuuuuuuuuuuu11xx00000100000000000000
WDTTime-Out(HALT)*uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuxxuuuuuuuuuuuuuuuuuuuu
USB-Reset(Normal)1111111100000111000000000000000000000111000000000000000000000111000000000000000000000000uu000u00u1uu00000uu0u000
USB-Reset(HALT)1111111100000111000000000000000000000111000000000000000000000111000000000000000000000000uu000u00u1uu00000uu0u000
²*²standsfor²warmreset²²u²standsfor²unchanged²²x²standsfor²unknown²
Timer/EventCounter
Twotimer/eventcounters(TMR0,TMR1)areimple-mentedinthemicrocontroller.TheTimer/EventCounter0containsan8-bitprogrammablecount-upcounterandtheclockmaycomesfromanexternalsourceorfromfSYS/4.BitNo.0~2,53467
Label¾TETONTM0TM1
Unusedbit,readas²0²
TodefinetheTMR0activeedgeofTimer/EventCounter0(0=activeonlowtohigh;1=activeonhightolow)
Toenable/disabletimer0counting(0=disabled;1=enabled)Todefinetheoperatingmode
01=Eventcountmode(externalclock)10=Timermode(internalclock)
11=Pulsewidthmeasurementmode00=Unused
TMR0C(0EH)Register
BitNo.0~2,53467
Label¾TETONTM0TM1
Unusedbit,readas²0²
TodefinetheTMR1activeedgeofTimer/EventCounter1(0=activeonlowtohigh;1=activeonhightolow)
Toenable/disabletimer1counting(0=disabled;1=enabled)Todefinetheoperatingmode
01=Eventcountmode(externalclock)10=Timermode(internalclock)
11=Pulsewidthmeasurementmode00=Unused
TMR1C(11H)Register
Rev.1.20
14
October24,2005
Function
TheTimer/EventCounter1containsan16-bitprogram-mablecount-upcounterandtheclockmaycomefromanexternalsourceorfromthesystemclockdividedby4.
Function
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HT82K95E/HT82K95ATimer/EventCounter0Timer/EventCounter1
Usingtheinternalclocksource,thereisonly1referencetime-baseforTimer/EventCounter0.TheinternalclocksourceiscomingfromfSYS/4.
Theexternalclockinputallowstheusertocountexter-nalevents,measuretimeintervalsorpulsewidths.Usingtheinternalclocksource,thereisonly1referencetime-baseforTimer/EventCounter1.TheinternalclocksourceiscomingfromfSYS/4.Theexternalclockinputallowstheusertocountexternalevents,measuretimeintervalsorpulsewidths.
Thereare2registersrelatedtotheTimer/EventCounter0;TMR0([0DH]),TMR0C([0EH]).Twophysicalregis-tersaremappedtoTMR0location;writingTMR0makesthestartingvaluebeplacedintheTimer/EventCounter0preloadregisterandreadingTMR0getsthecontentsoftheTimer/EventCounter0.TheTMR0Cisatimer/eventcountercontrolregister,whichdefinessomeoptions.
Thereare3registersrelatedtoTimer/EventCounter1;TMR1H(0FH),TMR1L(10H),TMR1C(11H).WritingTMR1Lwillonlyputthewrittendatatoaninternallower-orderbytebuffer(8bits)andwritingTMR1Hwilltransferthespecifieddataandthecontentsofthelower-orderbytebuffertoTMR1HandTMR1Lpreloadregisters,respectively.TheTimer/EventCounter1preloadregisterischangedbyeachwritingTMR1Hop-erations.ReadingTMR1HwilllatchthecontentsofTMR1HandTMR1Lcounterstothedestinationandthelower-orderbytebuffer,respectively.ReadingtheTMR1Lwillreadthecontentsofthelower-orderbytebuffer.TheTMR1CistheTimer/EventCounter1controlregister,whichdefinestheoperatingmode,countingen-ableordisableandactiveedge.
TheTM0,TM1bitsdefinetheoperatingmode.Theeventcountmodeisusedtocountexternalevents,whichmeanstheclocksourcecomesfromanexternal(TMR0/TMR1)pin.Thetimermodefunctionsasanor-maltimerwiththeclocksourcecomingfromthefSYS/4(Timer0/Timer1).Thepulsewidthmeasurementmodecanbeusedtocountthehighorlowleveldurationoftheexternalsignal(TMR0/TMR1).ThecountingisbasedonthefSYS/4(Timer0/Timer1).
Intheeventcountortimermode,oncetheTimer/EventCounter0/1startscounting,itwillcountfromthecurrentcontentsintheTimer/EventCounter0/1toFFHorFFFFH.Onceoverflowoccurs,thecounterisreloadedfromtheTimer/EventCounter0/1preloadregisterandgeneratestheinterruptrequestflag(T0F/T1F;bit5/6ofINTC)atthesametime.
InthepulsewidthmeasurementmodewiththeTONandTEbitsequaltoone,oncetheTMR0/TMR1hasre-ceivedatransientfromlowtohigh(orhightolowiftheTEbitsis²0²)itwillstartcountinguntiltheTMR0/TMR1returnstotheoriginallevelandresetstheTON.ThemeasuredresultwillremainintheTimer/EventCounter0/1eveniftheactivatedtransientoccursagain.Inotherwords,onlyonecyclemeasurementcanbedone.UntilsettingtheTON,thecyclemeasurementwillfunctionagainaslongasitreceivesfurthertransientpulse.Notethat,inthisoperatingmode,theTimer/EventCounter0/1startscountingnotaccordingtothelogiclevelbutaccordingtothetransientedges.Inthecaseofcounteroverflows,thecounter0/1isreloadedfromtheTimer/EventCounter0/1preloadregisterandissuestheinterruptrequestjustliketheothertwomodes.Toen-ablethecountingoperation,thetimerONbit(TON;bit4
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HT82K95E/HT82K95AofTMR0C/TMR1C)shouldbesetto1.Inthepulsewidthmeasurementmode,theTONwillbeclearedautomati-callyafterthemeasurementcycleiscompleted.ButintheothertwomodestheTONcanonlyberesetbyin-structions.TheoverflowoftheTimer/EventCounter0/1isoneofthewake-upsources.Nomatterwhattheoper-ationmodeis,writinga0toET0I/ET1Icandisablethecorrespondinginterruptservices.
InthecaseofTimer/EventCounter0/1OFFcondition,writingdatatotheTimer/EventCounter0/1preloadreg-isterwillalsoreloadthatdatatotheTimer/EventCoun-ter0/1.ButiftheTimer/EventCounter0/1isturnedon,datawrittentoitwillonlybekeptintheTimer/EventCounter0/1preloadregister.TheTimer/EventCounter0/1willstilloperateuntiloverflowoccurs(aTimer/EventCounter0/1reloadingwilloccuratthesametime).WhentheTimer/EventCounter0/1(readingTMR0/TMR1)isread,theclockwillbeblockedtoavoiderrors.Asclockblockingmayresultsinacountingerror,thismustbetakenintoconsiderationbytheprogram-mer.
Input/OutputPorts
Thereare32bidirectionalinput/outputlinesinthemicrocontroller,labeledfromPAtoPD,whicharemappedtothedatamemoryof[12H],[14H],[16H]and[18H]respectively.AlloftheseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,thatis,theinputsmustbereadyattheT2risingedgeofinstruction²MOVA,[m]²(m=12H,14H,16Hor18H).Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.
EachI/Olinehasitsowncontrolregister(PAC,PBC,PCC,PDC)tocontroltheinput/outputconfiguration.Withthiscontrolregister,CMOS/NMOS/PMOSoutput
orSchmitttriggerinputwithorwithoutpull-highresistorstructurescanbereconfigureddynamicallyundersoft-warecontrol.Tofunctionasaninput,thecorrespondinglatchofthecontrolregistermustwritea²1².Theinputsourcealsodependsonthecontrolregister.Ifthecon-trolregisterbitis²1²,theinputwillreadthepadstate.Ifthecontrolregisterbitis²0²,thecontentsofthelatcheswillmovetotheinternalbus.Thelatterispossibleinthe²read-modify-write²instruction.Foroutputfunction,CMOS/NMOS/PMOSconfigurationscanbeselected(NMOSandPMOSareavailableforPAonly).Thesecontrolregistersaremappedtolocations13H,15H,17Hand19H.
Afterachipreset,theseinput/outputlinesremainathighlevelsorfloatingstate(dependingonthepull-highop-tions).Eachbitoftheseinput/outputlatchescanbesetorclearedby²SET[m].i²and²CLR[m].i²(m=12H,14H,16Hor18H)instructions.
Someinstructionsfirstinputdataandthenfollowtheoutputoperations.Forexample,²SET[m].i²,²CLR[m].i²,²CPL[m]²,²CPLA[m]²readtheentireportstatesintotheCPU,executethedefinedoperations(bit-operation),andthenwritetheresultsbacktothelatchesortheaccumulator.
EachlineofalltheI/Oportshavethecapabilityofwak-ingupthedevice.
Therearepull-high(PAonly)optionsavailableforI/Olines.Oncethepull-highoptionofanI/Olineisselected,theI/Olinehavepull-highresistor.Otherwise,thepull-highresistorisabsent.Itshouldbenotedthatanon-pull-highI/Olineoperatingininputmodewillcauseafloatingstate.
ItisrecommendedthatunusedornotbondedoutI/Olinesshouldbesetasoutputpinsbysoftwareinstructiontoavoidconsumingpowerunderinputfloatingstate.
Input/OutputPorts
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HT82K95E/HT82K95ALowVoltageReset-LVR
Themicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebat-tery,theLVRwillautomaticallyresetthedeviceinter-nally.
TheLVRincludesthefollowingspecifications:
·ForavalidLVRsignal,alowvoltagei.e.avoltagein
SuspendWake-UpandRemoteWake-Up
IfthereisnosignalontheUSBbusforover3ms,theHT82K95E/HT82K95Awillgointosuspendmode.TheSuspendline(bit0oftheUSC)willbesetto²1²andaUSBinterruptistriggeredtoindicatethattheHT82K95E/HT82K95Ashouldjumptothesuspendstatetomeetthe500mAUSBsuspendcurrentspec.Inordertomeetthe500mAsuspendcurrent,thefirm-wareshoulddisabletheUSBclockbyclearingtheUSBCKEN(bit3oftheSCC)to²0².Thesuspendcur-rentis400mA.
Usercanfurtherdecreasethesuspendcurrentto250mAbysettingtheSUSP2(bit4oftheSCC).ButiftheSUSP2isset,usershouldmakesurenottoenabletheLVROPToption,otherwisetheHT82K95E/HT82K95Awillbereset.
Whentheresumesignalissentoutbythehost,theHT82K95E/HT82K95AwillwakeuptheMCUbyUSBin-terruptandtheResumeline(bit3oftheUSC)isset.InordertomaketheHT82K95E/HT82K95Afunctionprop-erly,thefirmwaremustsettheUSBCKEN(bit3oftheSCC)to²1²andcleartheSUSP2(bit4oftheSCC).SincetheResumesignalwillbeclearedbeforetheIdlesignalissentoutbythehost,theSuspendline(bit0oftheUSC)willbesetto²0².SowhentheMCUisdetect-ingtheSuspendline(bit0ofUSC),theResumelineshouldberememberedandtakenintoconsideration.Afterfinishingtheresumesignal,thesuspendlinewillgoinactiveandaUSBinterruptistriggered.Thefollow-ingisthetimingdiagram.
therangebetween0.9V~VLVRmustexistforgreaterthan1ms.Ifthelowvoltagestatedoesnotexceed1ms,theLVRwillignoreitanddonotperformaresetfunction.
·TheLVRusesthe²OR²functionwiththeexternal
RESsignaltoperformchipreset.
TherelationshipbetweenVDDandVLVRisshownbelow.
Note:
VOPRisthevoltagerangeforproperchipopera-tionat4MHzsystemclock.
LowVoltageReset
Note:
*1.Tomakesurethatthesystemoscillatorhasstabilized,theSSTprovidesanextradelayof1024system
clockpulsesbeforeenteringthenormaloperation.*2.Sincelowvoltagehastobemaintainedforover1msinitsoriginalstate,thereforethere¢sa1msdelaybeforeenteringtheresetmode
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HT82K95E/HT82K95AToConfiguretheHT82K95E/HT82K95AasPS2De-vice
TheHT82K95E/HT82K95AcanbeconfiguredasaUSBinterfaceorPS2interfacedevice,byconfiguringtheSPS2(bit4ofUSR)andSUSB(bit5oftheUSR).IfSPS2=1,andSUSB=0,theHT82K95E/HT82K95AisconfiguredasaPS2interface,pinUSBD-isconfiguredasaPS2DatapinandUSBD+isconfiguredasaPS2Clkpin.UsercaneasilyreadorwritetothePS2DataorPS2ClkpinbyaccessingthecorrespondingbitPS2DAI(bit4oftheUSC),PS2CKI(bit5oftheUSC),PS2DAO(bit6oftheUSC)andS2CKO(bit7oftheUSC)respec-tively.
Usershouldmakesurethatinordertoreadthedataproperly,thecorrespondingoutputbitmustbesetto²1².Forexample,ifitisdesiredtoreadthePS2DatabyreadingPS2DAI,thePS2DAOshouldsetto²1².Other-wiseitisalwaysreadas²0².
IfSPS2=0,andSUSB=1,theHT82K95E/HT82K95AisconfiguredasaUSBinterface.BoththeUSBD-andUSBD+isdrivenbytheSIEoftheHT82K95E/HT82K95A.UsercanonlywriteorreadtheUSBdatathroughthecorrespondingFIFO.BothSPS2andSUSBdefaultis²0².
ThedevicewithremotewakeupfunctioncanwakeuptheUSBHostbysendingawake-uppulsethroughRMWK(bit1oftheUSC).OncetheUSBHostreceivesawake-upsignalfromtheHT82K95E/HT82K95A,itwillsendaResumesignaltothedevice.Thetimingisasfol-lows:
USBInterface
Therearetenregisters,includingPIPE_CTRL(41Hinbank1),AWR(address+remotewake-up42Hinbank1),STALL(43Hinbank1),PIPE(44Hinbank1),SIES(45Hinbank1),MISC(46Hinbank1),Endpt_EN(47Hinbank1),FIFO0(48Hinbank1),FIFO1(49Hinbank1),andFIFO2(4AHinbank1)usedfortheUSBfunction.AWRregistercontainscurrentaddressandaremotewakeupfunctioncontrolbit.TheinitialvalueofAWRis²00H².TheaddressvalueextractedfromtheUSBcommandisnottobeloadedintothisregisteruntiltheSETUPstageiscompleted.BitNo.07~1
LabelWKENAD6~AD0
R/WWW
Remotewake-upenable/disableUSBdeviceaddress
AWR(42H)Register
STALLandPIPE,PIPE_CTRL,Endpt_ENRegisters
PIPEregisterrepresentswhethertheendpointcorrespondingisaccessedbyhostornot.AfterACT_ENsignalbeingsentout,MCUcancheckwhichendpointhadbeenaccessed.Thisregisterissetonlyafterthetimewhenhostaccessthecorrespondingendpoint.
STALLregistershowswhethertheendpointcorrespondingworksornot.Assoonastheendpointworkimproperly,thebitcorrespondingmustbeset.
PIPE_CTRLRegisterisusedforconfiguringIN(Bit=1)orOUT(Bit=0)Pipe.ThedefaultisdefineINpipe.WhereBit0(DATA0)ofthePIPE_CTRLRegisterisusedtosettingthedatatoggleofanyendpoint(exceptendpoint0)usingdatatogglestothevalueDATA0.Oncetheuserwanttheanyendpoint(exceptendpoint0)usingdatatogglestothevalueDATA0.theusercanoutputaLOWpulsetothisbit.TheLOWpulseperiodmustatleast10instructioncycle.Endpt_ENRegisterisusedtoenableordisablethecorrespondingendpoint(exceptendpoint0)EnableEndpoint(Bit=1)ordisableEndpoint(Bit=0)
Function
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HT82K95E/HT82K95AThebitmapsarelistasfollows:
RegisterNamePIPE_CTRLSTALLPIPEEndpt_EN
R/WR/WR/WRR/W
RegisterAddress01000001B01000011B01000100B01000001B
Bit7~Bit3Reserved
¾¾¾¾
Bit2Pipe2Pipe2Pipe2Pipe2
Bit1Pipe1Pipe1Pipe1Pipe1
Bit0Pipe0Pipe0Pipe0Pipe0
DefaultValue00000111000001110000000000000111
PIPE_CTRL(41H),STALL(43H),PIPE(44H)andEndpt_EN(47H)Registers
TheSIESRegisterisusedtoindicatethepresentsignalstatewhichtheSIEreceivesandalsodefineswhethertheSIEhastochangethedeviceaddressautomatically.
Bit7
Func.R/WReg_Adr
NMIR/W
Bit6EOTR
Bit5CRC_ERRR/W
Bit4NAKR
01000101B
SIES(45H)RegisterTable
Func.Name
R/W
Description
ThisbitisusedtoconfiguretheSIEtoautomaticallychangethedeviceaddresswiththevalueoftheAddress+Remote_WakeUpRegister(42H).
Whenthisbitissetto²1²byF/W,theSIEwillupdatethedeviceaddresswiththevalueoftheAddress+Remote_WakeUpRegister(42H)afterthePCHosthassuccessfullyreadthedatafromthedevicebytheINoperation.TheSIEwillclearthebitafterupdat-ingthedeviceaddress.Otherwise,whenthisbitisclearedto²0²,theSIEwillupdatethedeviceaddressimmediatelyafteranaddressiswrittentotheAddress+Re-mote_WakeUpRegister(42H)Default0
ThisbitisusedtoindicatethatsomeerrorshaveoccurredwhenaccessingtheFIFO0.ThisbitissetbySIEandclearedbyF/W.Default0
ThisbitisusedtoindicatethatanOUTtoken(exceptfortheOUTzerolength)hasbeenreceived.TheF/WclearthebitaftertheOUTdatahasbeenread.ThisbitwillalsobeclearedbytheSIEafterthenextvalidSETUPtokenisreceived.Default0
ThisbitisusedtoindicatethatthecurrentsignaltheUSBisreceivingfromthePCHostisINtoken.
ThisbitisusedtoindicatethattheSIEistransmittingNAKsignaltotheHostinre-sponsetothePCHostINorOUTtoken.
ThisbitisusedtoindicatethereareCRCerror(bit=1).Firmwaremustdosomethingtosavethedeviceandkeepitingoodcondition.ThisbitissetbySIEandclearedbyF/W.
Endoftransactionflag,normalstatusis1.Ifsuspend=¢1¢line&EOT=¢0¢indicatesthatsomethingiswrongintheUSBInterface.Firmwarein-chargemustdosomethingtosavethedeviceandkeepitingoodcondition.
ThisbitisusedtocontrolwhethertheUSBinterruptisoutputtotheMCUinNAKre-sponsetothePCHostINorOUTtoken.
1:hasonlyUSBinterrupt,dataistransmittedtothePChostordataisreceivedfromthePCHost
0:alwayshasUSBinterruptiftheUSBaccessesFIFO0Default0
SIESFunctionTable
Rev.1.20
19
October24,2005
Bit3INR
Bit2OUTR/W
Bit1F0_ERRR/W
Bit0Adr_setR/W
Adr_setR/W
F0_ErrR/W
OutR/W
INNAK
RR
CRC_ERRR/W
EOTR
NMIR/W
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HT82K95E/HT82K95AMISCregistercombinesacommandandstatustocontroldesiredendpointFIFOactionandtoshowthestatusofthedesiredendpointFIFO.TheMISCwillbeclearedbyUSBresetsignal.BitNo.0
LabelREQ
R/WR/W
Function
AftersettingtheotherstatusofthedesiredoneintheMISC,endpointFIFOcanberequestedbysettingthisbitto²1².Afterthejobhasbeendone,thisbithastobeclearedto²0².
ThisbitdefinesthedirectionofdatatransferringbetweenMCUandendpointFIFO.WhentheTXissetto²1²,thismeansthattheMCUwantstowritedatatotheend-pointFIFO.Afterthejobhasbeendone,thisbithastobeclearedto²0²beforetermi-natingrequesttorepresenttheendoftransferring.Forreadingaction,thisbithastobeclearedto²0²torepresentthatMCUwantstoreaddatafromtheendpointFIFOandhastobesetto²1²afterthejobisdone.
CleartherequestedendpointFIFO,eveniftheendpointFIFOisnotready.DefineswhichendpointFIFOisselected,SELP1,SELP0:00:endpointFIFO001:endpointFIFO110:endpointFIFO211:reserved
UsedtoshowthatthedatainendpointFIFOisaSETUPcommand.Thisbithastobeclearedbyfirmware.Thatistosay,eventheMCUisbusy,thedevicewillnotmissanySETUPcommandsfromthehost.
Readonlystatusbit,thisbitisusedtoindicatethatthedesiredendpointFIFOisreadytowork.
Usedtoindicatethata0-sizedpacketissentfromahosttotheMCU.Thisbitshouldbeclearedbyfirmware.
MISC(46H)Register
TheMCUcancommunicatewiththeendpointFIFObysettingthecorrespondingregisters,ofwhichaddressislistedinthefollowingtable.Afterreadingthecurrentdata,nextdatawillshowafter2ms,usedtochecktheendpointFIFOstatusandresponsetoMISCregister,ifread/writeactionisstillgoingon.
RegistersFIFO0FIFO1FIFO2
R/WR/WR/WR/W
Bank111
Address48H49H4AH
Bit7~Bit0Data7~Data0Data7~Data0Data7~Data0
1TXR/W
2CLEARR/W
43SELP1SELP0
R/W
5SCMDR/W
67
READYLEN0
RR/W
Therearesometimingconstrainsandusagesillustratedhere.BysettingtheMISCregister,MCUcanperformreading,writingandclearingactions.TherearesomeexamplesshowninthefollowingtableforendpointFIFOreading,writingandclearing.
Actions
ReadFIFO0sequenceWriteFIFO1sequence
CheckwhetherFIFO0canbereadornotCheckwhetherFIFO1canbewrittenornotRead0-sizedpacketsequenceformFIFO0Write0-sizedpacketsequencetoFIFO1Note:
MISCSettingFlowandStatus
00H®01H®delay2ms,check41H®read*fromFIFO0registerandchecknotready(01H)®03H®02H
0AH®0BH®delay2ms,check4BH®write*toFIFO1registerandchecknotready(0BH)®09H®08H
00H®01H®delay2ms,check41H(ready)or01H(notready)®00H0AH®0BH®delay2ms,check4BH(ready)or0BH(notready)®0AH00H®01H®delay2ms,check81H®readonce(01H)®03H®02H0AH®0BH®delay2ms,check0BH®0FH®0DH®08H
*:Thereare2msexistingbetween2readingactionorbetween2writingaction
Rev.1.2020October24,2005
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HT82K95E/HT82K95AThedefinitionsoftheUSB/PS2statusandcontrolregister(USC;1AH)areasshown.BitNo.0
LabelSUSP
R/WR
Function
Readonly,USBsuspendindication.Whenthisbitissetto²1²(setbySIE),itindi-catestheUSBbusenterssuspendmode.TheUSBinterruptisalsotriggeredonanychangesofthisbit.
USBremotewakeupcommand.ItissetbyMCUtoforcetheUSBhostleavingthesuspendmode.Whenthisbitissetto²1²,2msdelayforclearingthisbitto²0²isneededtoinsuretheRMWKcommandisacceptedbySIE.
USBresetindication.Thisbitisset/clearedbyUSBSIE.Thisbitisusedtodetectwhichbus(PS2orUSB)isattached.WhentheURSTissetto²1²,thisindicatesthataUSBresethasoccurred(theattachedbusisUSB)andaUSBinterruptwillbeini-tialized.
USBresumeindication.WhentheUSBleavesthesuspendmode,thisbitissetto²1²(setbySIE).Thisbitwillappear20mswaitingfortheMCUtodetect.WhentheRESUMEissetbytheSIE,aninterruptwillbegeneratedtowake-uptheMCU.Inor-dertodetectthesuspendstate,theMCUshouldsettheUSBCKENandclearSUSP2(inSCCregister)toenabletheSIEdetectingfunction.TheRESUMEwillbeclearedwhiletheSUSPisgoing²0².WhentheMCUisdetectingtheSUSP,theRE-SUME(wakes-uptheMCU)shouldberememberedandtakenintoconsideration.Readonly,USBD-/DATAinputReadonly,USBD+/CLKinput
DatafordrivingtheUSBD-/DATApinwhenworkingunder3DPS2mousefunction.(Default=²1²)
DatafordrivingtheUSBD+/CLKpinwhenworkingunder3DPS2mousefunction.(Default=²1²)
USC(1AH)Register
TheUSR(USBendpointinterruptstatusregister)registerisusedtoindicatewhichendpointisaccessedandtoselecttheserialbus(PS2orUSB).Theendpointrequestflags(EP0IF,EP1IFandEP2IF)areusedtoindicatewhichend-pointsareaccessed.Ifanendpointisaccessed,therelatedendpointrequestflagwillbesetto²1²andtheUSBinter-ruptwilloccur(iftheUSBinterruptisenabledandthestackisnotfull).Whentheactiveendpointrequestflagisserved,theendpointrequestflaghastobeclearedto²0².BitNo.0
LabelEP0IF
R/WR/W
Function
Whenthisbitissetto²1²(setbytheSIE),itindicatestheendpoint0isaccessedandaUSBinterruptwilloccur.Whentheinterrupthasbeenserved,thisbitshouldbeclearedbyfirmware.
Whenthisbitissetto²1²(setbytheSIE),itindicatestheendpoint1isaccessedandaUSBinterruptwilloccur.Whentheinterrupthasbeenserved,thisbitshouldbeclearedbyfirmware.
Whenthisbitissetto²1²(setbytheSIE),itindicatestheendpoint2isaccessedandaUSBinterruptwilloccur.Whentheinterrupthasbeenserved,thisbitshouldbeclearedbyfirmware.Reserved
ThePS2functionisselectedwhenthisbitissetto²1².(Default=²0²)TheUSBfunctionisselectedwhenthisbitissetto²1².(Default=²0²)
ThisflagisusedtoshowtheMCUisinUSBmode.(Bit=1)
ThisbitisR/WbyFWandwillbeclearedto²0²afterpower-onreset.(Default=²0²)
USR(1BH)Register
1RMWKW
2URSTR/W
3RESUMER
4567
PS2DAIPS2CKIPS2DAOPS2CKO
RRWW
1EP1IFR/W
23,57
EP2IF¾SPS2SUSBUSB_flag
R/W¾R/WR/WR/W
Rev.1.2021October24,2005
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HT82K95E/HT82K95AThereisasystemclockcontrolregisterimplementedtoselecttheclockusedintheMCU.ThisregisterconsistsoftheUSBclockcontrolbit(USBCKEN),secondsuspendmodecontrolbit(SUSP2)andsystemclockselection(SYSCLK).BitNo.2~0,73
Label¾
R/W¾
Undefined,shouldbeclearedto²0²
USBclockcontrolbit.Whenthisbitissetto²1²,itindicatesthattheUSBclockisen-abled.Otherwise,theUSBclockisturned-off.(Default=²0²)
Thisbitisusedfordecreasingpowerconsumptioninsuspendmode.Innormalmodecleanthisbit=0(Default=²0²)
InHALTmodesetthisbit=1fordecreasingpowerconsumption.
ThisflagisusedtoshowtheMCUisunderPS2mode.(Bit=1)
ThisbitisR/WbyFWandwillbeclearedto²0²afterpower-onreset.(Default=²0²)ThisbitisusedtospecifythesystemoscillatorfrequencyusedbytheMCU.Ifa6MHzcrystaloscillatororresonatorisused,thisbitshouldbesetto²1².Ifa12MHzcrystaloscillatororresonatorisused,thisbitshouldbeclearedto²0²(default).
SCC(1CH)Register
TableHighBytePointerforCurrentTableReadTBHP(Address0X1F)
RegisterTBHP(0X1F)Options
Thefollowingtableshowsallkindsofoptioninthemicrocontroller.Alloftheoptionsmustbedefinedtoensurepropersystemfunctioning.
No.1234567101112131415
Chiplockbit(bybit)
PA0~PA7pull-highresistorenabledordisabled(bybit)PB0~PB7pull-highresistorenabledordisabled(bynibble)PC0~PC7pull-highresistorenabledordisabled(bynibble)PD0~PD7pull-highresistorenabledordisabled(bynibble)LVRenableordisableWDTenableordisable
WDTclocksource:fSYS/4orWDTOSC²CLRWDT²instruction(s):1or2
PA0~PA7outputstructures:CMOS/NMOSopen-drain/PMOSopen-drain(bybit)PA0~PA7wake-upenabledordisabled(bybit)PB0~PB7wake-upenabledordisabled(bynibble)PC0~PC7wake-upenabledordisabled(bynibble)PD0~PD7wake-upenabledordisabled(bynibble)TBHPenableordisable(defaultdisable)
Option
Bits3~0
LabelsPGC3~PGC0
Read/Write
R
Option¾
Functions
Storecurrenttablereadbit11~bit8dataFunction
USBCKENR/W
4SUSP2R/W
5PS2_flagR/W
6SYSCLKR/W
Rev.1.2022October24,2005
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HT82K95E/HT82K95AApplicationCircuits
CrystalorCeramicResonatorforMultipleI/OApplications
Note:
TheresistanceandcapacitanceforresetcircuitshouldbedesignedinsuchawayastoensurethattheVDDisstableandremainswithinavalidoperatingvoltagerangebeforebringingREStohigh.X1canuse6MHzor12MHz,X1ascloseOSC1&OSC2aspossible.Componentswith*areusedforEMCissue.Componentswith**areusedforresonatoronly.Componentswith***areusedfor12MHzapplication.
Rev.1.2023October24,2005
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HT82K95E/HT82K95AInstructionSetSummary
MnemonicArithmeticADDA,[m]ADDMA,[m]ADDA,xADCA,[m]ADCMA,[m]SUBA,xSUBA,[m]SUBMA,[m]SBCA,[m]SBCMA,[m]DAA[m]
AdddatamemorytoACCAddACCtodatamemoryAddimmediatedatatoACC
AdddatamemorytoACCwithcarryAddACCtodatamemorywithcarrySubtractimmediatedatafromACCSubtractdatamemoryfromACC
SubtractdatamemoryfromACCwithresultindatamemorySubtractdatamemoryfromACCwithcarry
SubtractdatamemoryfromACCwithcarryandresultindatamemoryDecimaladjustACCforadditionwithresultindatamemory
11(1)111(1)111(1)11(1)1(1)
Z,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OV
C
Description
InstructionCycle
FlagAffected
LogicOperationANDA,[m]ORA,[m]XORA,[m]ANDMA,[m]ORMA,[m]XORMA,[m]ANDA,xORA,xXORA,xCPL[m]CPLA[m]
ANDdatamemorytoACCORdatamemorytoACC
Exclusive-ORdatamemorytoACCANDACCtodatamemoryORACCtodatamemory
Exclusive-ORACCtodatamemoryANDimmediatedatatoACCORimmediatedatatoACC
Exclusive-ORimmediatedatatoACCComplementdatamemory
ComplementdatamemorywithresultinACC
1111(1)1(1)1(1)1111(1)1
ZZZZZZZZZZZ
Increment&DecrementINCA[m]INC[m]DECA[m]DEC[m]RotateRRA[m]RR[m]RRCA[m]RRC[m]RLA[m]RL[m]RLCA[m]RLC[m]DataMoveMOVA,[m]MOV[m],AMOVA,xBitOperationCLR[m].iSET[m].i
ClearbitofdatamemorySetbitofdatamemory
1(1)1(1)
NoneNone
MovedatamemorytoACCMoveACCtodatamemoryMoveimmediatedatatoACC
11(1)1
NoneNoneNone
RotatedatamemoryrightwithresultinACCRotatedatamemoryright
RotatedatamemoryrightthroughcarrywithresultinACCRotatedatamemoryrightthroughcarryRotatedatamemoryleftwithresultinACCRotatedatamemoryleft
RotatedatamemoryleftthroughcarrywithresultinACCRotatedatamemoryleftthroughcarry
11(1)11(1)11(1)11(1)
NoneNoneCCNoneNoneCC
IncrementdatamemorywithresultinACCIncrementdatamemory
DecrementdatamemorywithresultinACCDecrementdatamemory
11(1)11(1)
ZZZZ
Rev.1.2024October24,2005
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HT82K95E/HT82K95AMnemonicBranchJMPaddrSZ[m]SZA[m]SZ[m].iSNZ[m].iSIZ[m]SDZ[m]SIZA[m]SDZA[m]CALLaddrRETRETA,xRETITableRead
TABRDC[m](5)ReadROMcode(locatebyTBLPandTBHP)todatamemoryandTBLHTABRDC[m](6)ReadROMcode(currentpage)todatamemoryandTBLH
ReadROMcode(lastpage)todatamemoryandTBLHTABRDL[m]MiscellaneousNOP
CLR[m]SET[m]CLRWDTCLRWDT1CLRWDT2SWAP[m]SWAPA[m]HALTNote:
Nooperation
CleardatamemorySetdatamemory
ClearWatchdogTimerPre-clearWatchdogTimerPre-clearWatchdogTimerSwapnibblesofdatamemory
SwapnibblesofdatamemorywithresultinACCEnterpowerdownmode
11(1)1(1)1111(1)11
NoneNoneNoneTO,PDFTO(4),PDF(4)TO(4),PDF(4)
NoneNoneTO,PDF
2(1)2(1)2(1)
NoneNoneNone
Jumpunconditionally
Skipifdatamemoryiszero
SkipifdatamemoryiszerowithdatamovementtoACCSkipifbitiofdatamemoryiszeroSkipifbitiofdatamemoryisnotzeroSkipifincrementdatamemoryiszeroSkipifdecrementdatamemoryiszero
SkipifincrementdatamemoryiszerowithresultinACCSkipifdecrementdatamemoryiszerowithresultinACCSubroutinecall
Returnfromsubroutine
ReturnfromsubroutineandloadimmediatedatatoACCReturnfrominterrupt
21(2)1(2)1(2)1(2)1(3)1(3)1(2)1(2)2222
NoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone
Description
InstructionCycle
FlagAffected
x:Immediatedatam:DatamemoryaddressA:Accumulatori:0~7numberofbits
addr:ProgrammemoryaddressÖ:Flagisaffected-:Flagisnotaffected
(1)
:IfaloadingtothePCLregisteroccurs,theexecutioncycleofinstructionswillbedelayedforonemorecycle(foursystemclocks).
:Ifaskippingtothenextinstructionoccurs,theexecutioncycleofinstructionswillbedelayedforonemorecycle(foursystemclocks).Otherwisetheoriginalinstructioncycleisunchanged.:
and(2)
:Theflagsmaybeaffectedbytheexecutionstatus.IftheWatchdogTimerisclearedbyexecutingthe²CLRWDT1²or²CLRWDT2²instruction,theTOandPDFarecleared.OtherwisetheTOandPDFflagsremainunchanged.:²ROMcodeTBHPoption²isenabled:²ROMcodeTBHPoption²isdisabled
(2)
(3)(1)(4)
(5)(6)
Rev.1.2025October24,2005
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HT82K95E/HT82K95AInstructionDefinition
ADCA,[m]DescriptionOperationAffectedflag(s)
TO¾
ADCMA,[m]DescriptionOperationAffectedflag(s)
TO¾
ADDA,[m]DescriptionOperationAffectedflag(s)
TO¾
ADDA,xDescriptionOperationAffectedflag(s)
TO¾
ADDMA,[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
PDF¾
OVÖ
ZÖ
ACÖ
CÖ
Adddatamemoryandcarrytotheaccumulator
Thecontentsofthespecifieddatamemory,accumulatorandthecarryflagareaddedsi-multaneously,leavingtheresultintheaccumulator.ACC¬ACC+[m]+C
Addtheaccumulatorandcarrytodatamemory
Thecontentsofthespecifieddatamemory,accumulatorandthecarryflagareaddedsi-multaneously,leavingtheresultinthespecifieddatamemory.[m]¬ACC+[m]+C
Adddatamemorytotheaccumulator
Thecontentsofthespecifieddatamemoryandtheaccumulatorareadded.Theresultisstoredintheaccumulator.ACC¬ACC+[m]
Addimmediatedatatotheaccumulator
Thecontentsoftheaccumulatorandthespecifieddataareadded,leavingtheresultintheaccumulator.ACC¬ACC+x
Addtheaccumulatortothedatamemory
Thecontentsofthespecifieddatamemoryandtheaccumulatorareadded.Theresultisstoredinthedatamemory.[m]¬ACC+[m]
Rev.1.2026October24,2005
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HT82K95E/HT82K95AANDA,[m]DescriptionOperationAffectedflag(s)
TO¾
ANDA,xDescriptionOperationAffectedflag(s)
TO¾
ANDMA,[m]DescriptionOperationAffectedflag(s)
TO¾
CALLaddrDescription
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
LogicalANDaccumulatorwithdatamemory
Dataintheaccumulatorandthespecifieddatamemoryperformabitwiselogical_ANDop-eration.Theresultisstoredintheaccumulator.ACC¬ACC²AND²[m]
LogicalANDimmediatedatatotheaccumulator
Dataintheaccumulatorandthespecifieddataperformabitwiselogical_ANDoperation.Theresultisstoredintheaccumulator.ACC¬ACC²AND²x
LogicalANDdatamemorywiththeaccumulator
Datainthespecifieddatamemoryandtheaccumulatorperformabitwiselogical_ANDop-eration.Theresultisstoredinthedatamemory.[m]¬ACC²AND²[m]
Subroutinecall
Theinstructionunconditionallycallsasubroutinelocatedattheindicatedaddress.Theprogramcounterincrementsoncetoobtaintheaddressofthenextinstruction,andpushesthisontothestack.Theindicatedaddressisthenloaded.Programexecutioncontinueswiththeinstructionatthisaddress.Stack¬ProgramCounter+1ProgramCounter¬addr
OperationAffectedflag(s)
TO¾
CLR[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
Z¾
AC¾
C¾
Cleardatamemory
Thecontentsofthespecifieddatamemoryareclearedto0.[m]¬00H
PDF¾
OV¾
Z¾
AC¾
C¾
Rev.1.2027October24,2005
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HT82K95E/HT82K95ACLR[m].iDescriptionOperationAffectedflag(s)
TO¾
CLRWDTDescriptionOperationAffectedflag(s)
TO0
CLRWDT1Description
PDF0
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
Clearbitofdatamemory
Thebitiofthespecifieddatamemoryisclearedto0.[m].i¬0
ClearWatchdogTimer
TheWDTiscleared(clearstheWDT).Thepowerdownbit(PDF)andtime-outbit(TO)arecleared.
WDT¬00H
PDFandTO¬0
PreclearWatchdogTimer
TogetherwithCLRWDT2,clearstheWDT.PDFandTOarealsocleared.Onlyexecutionofthisinstructionwithouttheotherpreclearinstructionjustsetstheindicatedflagwhichim-pliesthisinstructionhasbeenexecutedandtheTOandPDFflagsremainunchanged.WDT¬00H*
PDFandTO¬0*
OperationAffectedflag(s)
TO0*
CLRWDT2Description
PDF0*
OV¾
Z¾
AC¾
C¾
PreclearWatchdogTimer
TogetherwithCLRWDT1,clearstheWDT.PDFandTOarealsocleared.Onlyexecutionofthisinstructionwithouttheotherpreclearinstruction,setstheindicatedflagwhichim-pliesthisinstructionhasbeenexecutedandtheTOandPDFflagsremainunchanged.WDT¬00H*
PDFandTO¬0*
OperationAffectedflag(s)
TO0*
CPL[m]DescriptionOperationAffectedflag(s)
TO¾
PDF0*
OV¾
Z¾
AC¾
C¾
Complementdatamemory
Eachbitofthespecifieddatamemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andvice-versa.[m]¬[m]
PDF¾
OV¾
ZÖ
AC¾
C¾
Rev.1.2028October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ACPLA[m]Description
Complementdatamemoryandplaceresultintheaccumulator
Eachbitofthespecifieddatamemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andvice-versa.Thecomplementedresultisstoredintheaccumulatorandthecontentsofthedatamemoryremainunchanged.ACC¬[m]OperationAffectedflag(s)
TO¾
DAA[m]Description
PDF¾
OV¾
ZÖ
AC¾
C¾
Decimal-Adjustaccumulatorforaddition
TheaccumulatorvalueisadjustedtotheBCD(BinaryCodedDecimal)code.Theaccumu-latorisdividedintotwonibbles.EachnibbleisadjustedtotheBCDcodeandaninternalcarry(AC1)willbedoneifthelownibbleoftheaccumulatorisgreaterthan9.TheBCDad-justmentisdonebyadding6totheoriginalvalueiftheoriginalvalueisgreaterthan9oracarry(ACorC)isset;otherwisetheoriginalvalueremainsunchanged.Theresultisstoredinthedatamemoryandonlythecarryflag(C)maybeaffected.IfACC.3~ACC.0>9orAC=1
then[m].3~[m].0¬(ACC.3~ACC.0)+6,AC1=ACelse[m].3~[m].0¬(ACC.3~ACC.0),AC1=0and
IfACC.7~ACC.4+AC1>9orC=1
then[m].7~[m].4¬ACC.7~ACC.4+6+AC1,C=1else[m].7~[m].4¬ACC.7~ACC.4+AC1,C=C
Operation
Affectedflag(s)
TO¾
DEC[m]DescriptionOperationAffectedflag(s)
TO¾
DECA[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
CÖ
Decrementdatamemory
Datainthespecifieddatamemoryisdecrementedby1.[m]¬[m]-1
Decrementdatamemoryandplaceresultintheaccumulator
Datainthespecifieddatamemoryisdecrementedby1,leavingtheresultintheaccumula-tor.Thecontentsofthedatamemoryremainunchanged.ACC¬[m]-1
Rev.1.2029October24,2005
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HT82K95E/HT82K95AHALTDescription
Enterpowerdownmode
Thisinstructionstopsprogramexecutionandturnsoffthesystemclock.ThecontentsoftheRAMandregistersareretained.TheWDTandprescalerarecleared.Thepowerdownbit(PDF)issetandtheWDTtime-outbit(TO)iscleared.ProgramCounter¬ProgramCounter+1PDF¬1TO¬0
Operation
Affectedflag(s)
TO0
INC[m]DescriptionOperationAffectedflag(s)
TO¾
INCA[m]DescriptionOperationAffectedflag(s)
TO¾
JMPaddrDescriptionOperationAffectedflag(s)
TO¾
MOVA,[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
Directlyjump
Theprogramcounterarereplacedwiththedirectly-specifiedaddressunconditionally,andcontrolispassedtothisdestination.ProgramCounter¬addr
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF1
OV¾
Z¾
AC¾
C¾
Incrementdatamemory
Datainthespecifieddatamemoryisincrementedby1[m]¬[m]+1
Incrementdatamemoryandplaceresultintheaccumulator
Datainthespecifieddatamemoryisincrementedby1,leavingtheresultintheaccumula-tor.Thecontentsofthedatamemoryremainunchanged.ACC¬[m]+1
Movedatamemorytotheaccumulator
Thecontentsofthespecifieddatamemoryarecopiedtotheaccumulator.ACC¬[m]
Rev.1.2030October24,2005
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HT82K95E/HT82K95AMOVA,xDescriptionOperationAffectedflag(s)
TO¾
MOV[m],ADescriptionOperationAffectedflag(s)
TO¾
NOPDescriptionOperationAffectedflag(s)
TO¾
ORA,[m]DescriptionOperationAffectedflag(s)
TO¾
ORA,xDescriptionOperationAffectedflag(s)
TO¾
ORMA,[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
ZÖ
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
Nooperation
Nooperationisperformed.Executioncontinueswiththenextinstruction.ProgramCounter¬ProgramCounter+1
PDF¾
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
Moveimmediatedatatotheaccumulator
The8-bitdataspecifiedbythecodeisloadedintotheaccumulator.ACC¬x
Movetheaccumulatortodatamemory
Thecontentsoftheaccumulatorarecopiedtothespecifieddatamemory(oneofthedatamemories).[m]¬ACC
LogicalORaccumulatorwithdatamemory
Dataintheaccumulatorandthespecifieddatamemory(oneofthedatamemories)per-formabitwiselogical_ORoperation.Theresultisstoredintheaccumulator.ACC¬ACC²OR²[m]
LogicalORimmediatedatatotheaccumulator
Dataintheaccumulatorandthespecifieddataperformabitwiselogical_ORoperation.Theresultisstoredintheaccumulator.ACC¬ACC²OR²x
LogicalORdatamemorywiththeaccumulator
Datainthedatamemory(oneofthedatamemories)andtheaccumulatorperformabitwiselogical_ORoperation.Theresultisstoredinthedatamemory.[m]¬ACC²OR²[m]
Rev.1.2031October24,2005
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HT82K95E/HT82K95ARETDescriptionOperationAffectedflag(s)
TO¾
RETA,xDescriptionOperationAffectedflag(s)
TO¾
RETIDescriptionOperationAffectedflag(s)
TO¾
RL[m]DescriptionOperationAffectedflag(s)
TO¾
RLA[m]DescriptionOperationAffectedflag(s)
TO¾
PDF¾
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
PDF¾
OV¾
Z¾
AC¾
C¾
Returnfromsubroutine
Theprogramcounterisrestoredfromthestack.Thisisa2-cycleinstruction.ProgramCounter¬Stack
Returnandplaceimmediatedataintheaccumulator
Theprogramcounterisrestoredfromthestackandtheaccumulatorloadedwiththespeci-fied8-bitimmediatedata.ProgramCounter¬StackACC¬x
Returnfrominterrupt
Theprogramcounterisrestoredfromthestack,andinterruptsareenabledbysettingtheEMIbit.EMIistheenablemaster(global)interruptbit.ProgramCounter¬StackEMI¬1
Rotatedatamemoryleft
Thecontentsofthespecifieddatamemoryarerotated1bitleftwithbit7rotatedintobit0.[m].(i+1)¬[m].i;[m].i:bitiofthedatamemory(i=0~6)[m].0¬[m].7
Rotatedatamemoryleftandplaceresultintheaccumulator
Datainthespecifieddatamemoryisrotated1bitleftwithbit7rotatedintobit0,leavingtherotatedresultintheaccumulator.Thecontentsofthedatamemoryremainunchanged.ACC.(i+1)¬[m].i;[m].i:bitiofthedatamemory(i=0~6)ACC.0¬[m].7
Rev.1.2032October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ARLC[m]DescriptionOperation
Rotatedatamemoryleftthroughcarry
Thecontentsofthespecifieddatamemoryandthecarryflagarerotated1bitleft.Bit7re-placesthecarrybit;theoriginalcarryflagisrotatedintothebit0position.[m].(i+1)¬[m].i;[m].i:bitiofthedatamemory(i=0~6)[m].0¬CC¬[m].7
Affectedflag(s)
TO¾
RLCA[m]Description
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Rotateleftthroughcarryandplaceresultintheaccumulator
Datainthespecifieddatamemoryandthecarryflagarerotated1bitleft.Bit7replacesthecarrybitandtheoriginalcarryflagisrotatedintobit0position.Therotatedresultisstoredintheaccumulatorbutthecontentsofthedatamemoryremainunchanged.ACC.(i+1)¬[m].i;[m].i:bitiofthedatamemory(i=0~6)ACC.0¬CC¬[m].7
Operation
Affectedflag(s)
TO¾
RR[m]DescriptionOperationAffectedflag(s)
TO¾
RRA[m]DescriptionOperationAffectedflag(s)
TO¾
RRC[m]DescriptionOperation
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Rotatedatamemoryright
Thecontentsofthespecifieddatamemoryarerotated1bitrightwithbit0rotatedtobit7.[m].i¬[m].(i+1);[m].i:bitiofthedatamemory(i=0~6)[m].7¬[m].0
Rotaterightandplaceresultintheaccumulator
Datainthespecifieddatamemoryisrotated1bitrightwithbit0rotatedintobit7,leavingtherotatedresultintheaccumulator.Thecontentsofthedatamemoryremainunchanged.ACC.(i)¬[m].(i+1);[m].i:bitiofthedatamemory(i=0~6)ACC.7¬[m].0
Rotatedatamemoryrightthroughcarry
Thecontentsofthespecifieddatamemoryandthecarryflagaretogetherrotated1bitright.Bit0replacesthecarrybit;theoriginalcarryflagisrotatedintothebit7position.[m].i¬[m].(i+1);[m].i:bitiofthedatamemory(i=0~6)[m].7¬CC¬[m].0
Affectedflag(s)
TO¾
Rev.1.20
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October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ARRCA[m]Description
Rotaterightthroughcarryandplaceresultintheaccumulator
Dataofthespecifieddatamemoryandthecarryflagarerotated1bitright.Bit0replacesthecarrybitandtheoriginalcarryflagisrotatedintothebit7position.Therotatedresultisstoredintheaccumulator.Thecontentsofthedatamemoryremainunchanged.ACC.i¬[m].(i+1);[m].i:bitiofthedatamemory(i=0~6)ACC.7¬CC¬[m].0
Operation
Affectedflag(s)
TO¾
SBCA,[m]DescriptionOperationAffectedflag(s)
TO¾
SBCMA,[m]DescriptionOperationAffectedflag(s)
TO¾
SDZ[m]Description
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Subtractdatamemoryandcarryfromtheaccumulator
Thecontentsofthespecifieddatamemoryandthecomplementofthecarryflagaresub-tractedfromtheaccumulator,leavingtheresultintheaccumulator.ACC¬ACC+[m]+C
Subtractdatamemoryandcarryfromtheaccumulator
Thecontentsofthespecifieddatamemoryandthecomplementofthecarryflagaresub-tractedfromtheaccumulator,leavingtheresultinthedatamemory.[m]¬ACC+[m]+C
Skipifdecrementdatamemoryis0
Thecontentsofthespecifieddatamemoryaredecrementedby1.Iftheresultis0,thenextinstructionisskipped.Iftheresultis0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruc-tion(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif([m]-1)=0,[m]¬([m]-1)
OperationAffectedflag(s)
TO¾
SDZA[m]Description
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DecrementdatamemoryandplaceresultinACC,skipif0
Thecontentsofthespecifieddatamemoryaredecrementedby1.Iftheresultis0,thenextinstructionisskipped.Theresultisstoredintheaccumulatorbutthedatamemoryremainsunchanged.Iftheresultis0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cy-cles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif([m]-1)=0,ACC¬([m]-1)
OperationAffectedflag(s)
TO¾
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Rev.1.2034October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ASET[m]DescriptionOperationAffectedflag(s)
TO¾
SET[m].iDescriptionOperationAffectedflag(s)
TO¾
SIZ[m]Description
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Setdatamemory
Eachbitofthespecifieddatamemoryissetto1.[m]¬FFH
Setbitofdatamemory
Bitiofthespecifieddatamemoryissetto1.[m].i¬1
Skipifincrementdatamemoryis0
Thecontentsofthespecifieddatamemoryareincrementedby1.Iftheresultis0,thefol-lowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif([m]+1)=0,[m]¬([m]+1)
OperationAffectedflag(s)
TO¾
SIZA[m]Description
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IncrementdatamemoryandplaceresultinACC,skipif0
Thecontentsofthespecifieddatamemoryareincrementedby1.Iftheresultis0,thenextinstructionisskippedandtheresultisstoredintheaccumulator.Thedatamemoryre-mainsunchanged.Iftheresultis0,thefollowinginstruction,fetchedduringthecurrentin-structionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif([m]+1)=0,ACC¬([m]+1)
OperationAffectedflag(s)
TO¾
SNZ[m].iDescription
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Skipifbitiofthedatamemoryisnot0
Ifbitiofthespecifieddatamemoryisnot0,thenextinstructionisskipped.Ifbitiofthedatamemoryisnot0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Other-wiseproceedwiththenextinstruction(1cycle).Skipif[m].i¹0
OperationAffectedflag(s)
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Rev.1.2035October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ASUBA,[m]DescriptionOperationAffectedflag(s)
TO¾
SUBMA,[m]DescriptionOperationAffectedflag(s)
TO¾
SUBA,xDescriptionOperationAffectedflag(s)
TO¾
SWAP[m]DescriptionOperationAffectedflag(s)
TO¾
SWAPA[m]DescriptionOperationAffectedflag(s)
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Subtractdatamemoryfromtheaccumulator
Thespecifieddatamemoryissubtractedfromthecontentsoftheaccumulator,leavingtheresultintheaccumulator.ACC¬ACC+[m]+1
Subtractdatamemoryfromtheaccumulator
Thespecifieddatamemoryissubtractedfromthecontentsoftheaccumulator,leavingtheresultinthedatamemory.[m]¬ACC+[m]+1
Subtractimmediatedatafromtheaccumulator
Theimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheaccumula-tor,leavingtheresultintheaccumulator.ACC¬ACC+x+1
Swapnibbleswithinthedatamemory
Thelow-orderandhigh-ordernibblesofthespecifieddatamemory(1ofthedatamemo-ries)areinterchanged.[m].3~[m].0«[m].7~[m].4
Swapdatamemoryandplaceresultintheaccumulator
Thelow-orderandhigh-ordernibblesofthespecifieddatamemoryareinterchanged,writ-ingtheresulttotheaccumulator.Thecontentsofthedatamemoryremainunchanged.ACC.3~ACC.0¬[m].7~[m].4ACC.7~ACC.4¬[m].3~[m].0
Rev.1.2036October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ASZ[m]Description
Skipifdatamemoryis0
Ifthecontentsofthespecifieddatamemoryare0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif[m]=0
OperationAffectedflag(s)
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SZA[m]Description
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MovedatamemorytoACC,skipif0
Thecontentsofthespecifieddatamemoryarecopiedtotheaccumulator.Ifthecontentsis0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruction(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif[m]=0
OperationAffectedflag(s)
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SZ[m].iDescription
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Skipifbitiofthedatamemoryis0
Ifbitiofthespecifieddatamemoryis0,thefollowinginstruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycycleisreplacedtogettheproperinstruc-tion(2cycles).Otherwiseproceedwiththenextinstruction(1cycle).Skipif[m].i=0
OperationAffectedflag(s)
TO¾
TABRDC[m]DescriptionOperationAffectedflag(s)
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TABRDC[m]DescriptionOperationAffectedflag(s)
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MovetheROMcode(locatebyTBLPandTBHP)toTBLHanddatamemory(ROMcodeTBHPisenabled)
ThelowbyteofROMcodeaddressedbythetablepointer(TBLPandTBHP)ismovedtothespecifieddatamemoryandthehighbytetransferredtoTBLHdirectly.[m]¬ROMcode(lowbyte)TBLH¬ROMcode(highbyte)
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MovetheROMcode(currentpage)toTBLHanddatamemory(ROMcodeTBHPisdis-abled)
ThelowbyteofROMcode(currentpage)addressedbythetablepointer(TBLP)ismovedtothespecifieddatamemoryandthehighbytetransferredtoTBLHdirectly.[m]¬ROMcode(lowbyte)TBLH¬ROMcode(highbyte)
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Rev.1.2037October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ATABRDL[m]DescriptionOperationAffectedflag(s)
TO¾
XORA,[m]DescriptionOperationAffectedflag(s)
TO¾
XORMA,[m]DescriptionOperationAffectedflag(s)
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XORA,xDescriptionOperationAffectedflag(s)
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MovetheROMcode(lastpage)toTBLHanddatamemory
ThelowbyteofROMcode(lastpage)addressedbythetablepointer(TBLP)ismovedtothedatamemoryandthehighbytetransferredtoTBLHdirectly.[m]¬ROMcode(lowbyte)TBLH¬ROMcode(highbyte)
LogicalXORaccumulatorwithdatamemory
DataintheaccumulatorandtheindicateddatamemoryperformabitwiselogicalExclu-sive_ORoperationandtheresultisstoredintheaccumulator.ACC¬ACC²XOR²[m]
LogicalXORdatamemorywiththeaccumulator
DataintheindicateddatamemoryandtheaccumulatorperformabitwiselogicalExclu-sive_ORoperation.Theresultisstoredinthedatamemory.The0flagisaffected.[m]¬ACC²XOR²[m]
LogicalXORimmediatedatatotheaccumulator
DataintheaccumulatorandthespecifieddataperformabitwiselogicalExclusive_ORop-eration.Theresultisstoredintheaccumulator.The0flagisaffected.ACC¬ACC²XOR²x
Rev.1.2038October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95APackageInformation
20-pinSOP(300mil)OutlineDimensions
SymbolABCC¢DEFGHa
Dimensionsinmil
Min.3942901449092¾43240°
Nom.¾¾¾¾¾50¾¾¾¾
Max.41930020510104¾¾381210°
Rev.1.2039October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95A28-pinSOP(300mil)OutlineDimensions
SymbolABCC¢DEFGHa
Dimensionsinmil
Min.3942901469792¾43240°
Nom.¾¾¾¾¾50¾¾¾¾
Max.41930020713104¾¾381210°
Rev.1.2040October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95A20-pinSSOP(209mil)OutlineDimensions
SymbolABCC¢DEFGHa
Dimensionsinmil
Min.291196927165¾420°
Nom.¾¾¾¾¾25.59¾¾¾¾
Max.3232201529573¾103488°
Rev.1.2041October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95A48-pinSSOP(300mil)OutlineDimensions
SymbolABCC¢DEFGHa
Dimensionsinmil
Min.395291861385¾42540°
Nom.¾¾¾¾¾25¾¾¾¾
Max.4202991263799¾1035128°
Rev.1.2042October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95AProductTapeandReelSpecifications
ReelDimensions
SOP20W
SymbolABCDT1T2
Description
ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth
SpaceBetweenFlangeReelThickness
Dimensionsinmm
330±162±1.513+0.5
-0.22±0.524.8+0.3
-0.230.2±0.2
SOP28W(300mil)
SymbolABCDT1T2
Description
ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth
SpaceBetweenFlangeReelThickness
Dimensionsinmm
330±162±1.513+0.5
-0.22±0.524.8+0.3
-0.230.2±0.2
Rev.1.2043October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ASSOP20N(209mil)
SymbolABCDT1T2
SSOP48W
SymbolABCDT1T2
Description
ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth
SpaceBetweenFlangeReelThickness
Dimensionsinmm
330±1100±0.113+0.5
-0.22±0.532.2+0.3
-0.238.2±0.2
Description
ReelOuterDiameterReelInnerDiameterSpindleHoleDiameterKeySlitWidth
SpaceBetweenFlangeReelThickness
Dimensionsinmm
330±162±1.513+0.5
-0.22±0.516.8+0.3
-0.222.2±0.2
Rev.1.2044October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ACarrierTapeDimensions
SOP20W
SymbolWPEFDD1P0P1A0B0K0tC
Description
CarrierTapeWidthCavityPitchPerforationPosition
CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch
CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth
CarrierTapeThicknessCoverTapeWidth
Dimensionsinmm
24+0.3
-0.112±0.11.75±0.111.5±0.11.5+0.11.5+0.254±0.12±0.110.8±0.113.3±0.13.2±0.10.3±0.0521.3
SOP28W(300mil)
SymbolWPEFDD1P0P1A0B0K0tC
CavityPitchPerforationPosition
CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch
CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth
CarrierTapeThicknessCoverTapeWidth
Description
CarrierTapeWidth
Dimensionsinmm
24±0.312±0.11.75±0.111.5±0.11.5+0.11.5+0.254±0.12±0.110.85±0.118.34±0.12.97±0.10.35±0.0121.3
Rev.1.2045October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ASSOP20N(209mil)
SymbolWPEFDD1P0P1A0B0K0tC
Description
CarrierTapeWidthCavityPitchPerforationPosition
CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch
CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepth
CarrierTapeThicknessCoverTapeWidth
Dimensionsinmm
16+0.3
-0.112±0.11.75±0.17.5±0.11.5+0.11.5+0.254±0.12±0.17.1±0.17.2±0.12±0.10.3±0.0513.3
Rev.1.2046October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95ASSOP48W
SymbolWPEFDD1P0P1A0B0K1K2tC
Description
CarrierTapeWidthCavityPitchPerforationPosition
CavitytoPerforation(WidthDirection)PerforationDiameterCavityHoleDiameterPerforationPitch
CavitytoPerforation(LengthDirection)CavityLengthCavityWidthCavityDepthCavityDepth
CarrierTapeThicknessCoverTapeWidth
Dimensionsinmm
32±0.316±0.11.75±0.114.2±0.12Min.1.5+0.254±0.12±0.112±0.116.2±0.12.4±0.13.2±0.10.35±0.0525.5
Rev.1.2047October24,2005
元器件交易网www.cecb2b.com
HT82K95E/HT82K95AHoltekSemiconductorInc.(Headquarters)
No.3,CreationRd.II,SciencePark,Hsinchu,TaiwanTel:886-3-563-1999Fax:886-3-563-11http://www.holtek.com.tw
HoltekSemiconductorInc.(TaipeiSalesOffice)
4F-2,No.3-2,YuanQuSt.,NankangSoftwarePark,Taipei115,TaiwanTel:886-2-2655-7070Fax:886-2-2655-7373
Fax:886-2-2655-7383(Internationalsaleshotline)
HoltekSemiconductorInc.(ShanghaiSalesOffice)
7thFloor,Building2,No.8,YiShanRd.,Shanghai,China200233Tel:021-85-5560Fax:021-85-0313
http://www.holtek.com.cn
HoltekSemiconductorInc.(ShenzhenSalesOffice)
43F,SEGPlaza,ShenNanZhongRoad,Shenzhen,China518031Tel:0755-8346-55Fax:0755-8346-5590ISDN:0755-8346-5591
HoltekSemiconductorInc.(BeijingSalesOffice)
Suite1721,JinyuTower,A129WestXuanWuMenStreet,XichengDistrict,Beijing,China100031Tel:010-61-0030,61-7751,61-7752Fax:010-61-0125
HolmateSemiconductor,Inc.(NorthAmericaSalesOffice)46712FremontBlvd.,Fremont,CA94538Tel:510-252-9880Fax:510-252-9885
http://www.holmate.com
CopyrightÓ2005byHOLTEKSEMICONDUCTORINC.
TheinformationappearinginthisDataSheetisbelievedtobeaccurateatthetimeofpublication.However,Holtekas-sumesnoresponsibilityarisingfromtheuseofthespecificationsdescribed.TheapplicationsmentionedhereinareusedsolelyforthepurposeofillustrationandHoltekmakesnowarrantyorrepresentationthatsuchapplicationswillbesuitablewithoutfurthermodification,norrecommendstheuseofitsproductsforapplicationthatmaypresentarisktohumanlifeduetomalfunctionorotherwise.Holtek¢sproductsarenotauthorizedforuseascriticalcomponentsinlifesupportdevicesorsystems.Holtekreservestherighttoalteritsproductswithoutpriornotification.Forthemostup-to-dateinformation,pleasevisitourwebsiteathttp://www.holtek.com.tw.
Rev.1.2048October24,2005
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