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专利名称：ADJUSTABLE DELAY CIRCUIT FOR
OPTIMIZING TIMING MARGIN
发明人：HIDEYUKI ICHIDA,RAGHUKIRAN
SREERAMANENI
申请号：US148454申请日：20150909
公开号：US20170070219A1公开日：20170309
专利附图：
摘要：The present invention relates to timing margin adjustment circuits usingadjustable delay circuits. An example adjustable delay circuit may include a signal line, an
output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits maybe configured to provide respective delay amounts that are different from each other,and where a first one of the plurality of delay circuits, which may be arranged mostadjacently to the output circuit, being smaller in delay amount than other ones of theplurality of delay circuits. Each of the plurality of delay circuits may include an input nodeand an output node, and a selected one of the plurality of delay circuits connected at itsinput node to the signal line and at its output node to the output circuit, the rest of theplurality of delay circuits being disconnected from the signal line and the output circuit.
申请人：Micron Technology, Inc.
地址：Boise ID US
国籍：US
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