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专利名称：Variable time delay circuit and method发明人：Baker Scott,Izumi Kawata申请号：US08/931995申请日：19970917公开号：US06121811A公开日：20000919
摘要：A high resolution variable time delay circuit is disclosed. In one embodiment, acurrent digital to analog converter (DAC) is used to sequentially charge two capacitorshaving similar capacitance construction. A threshold level capacitor provides thethreshold level to a comparator, and a ramping capacitor is used for ramping to thethreshold to provide a delay time. The comparator provides a delayed pulse using thethreshold level provided by the threshold level capacitor and the ramp provided by theramping capacitor. Thus, resolution is better than that provided by digital elementsalone. This circuit also automatically cancels errors due to capacitance variations and unitcurrent variation of the DAC introduced during the manufacturing process. In anotherembodiment a single capacitor is used in combination with two current DACs and acomparator to provide a controllable time delay.
申请人：CRYSTAL SEMICONDUCTOR CORPORATION
代理机构：Arnold White & Durkee
代理人：J. P. Violette
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