ATS52技术手册

Features

• Compatible with MCS-51® Products

• 8K Bytes of In-System Programmable (ISP) Flash Memory • 1000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources

• Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag

Description

The ATS52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combining a versatile 8-bit CPU with in system programmable Flash on a monolithicchip, the Atmel ATS52 is a powerful icrocontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The ATS52 provides the following tandard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a

full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the ATS52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

Pin Configurations

Block Diagram

Pin Description

VCC

Supply voltage. GND Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance Inputs.

Port 0 can also be configured to be the multiplexed loworder address/data bus during ccesses to external program and data memory. In this mode, P0 has int -ernal pullups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur -ing program verification.External pullups are required during program veri- fication. Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the ti -mer/counter 2 exte- rnal count input (P1.0/T2) and the timer/counter 2 trigger input(P1.1/T2EX), respectively, as shown in the following table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin P1.0 P1.1 P1.5 P1.6 P1.7 Port 2

Alternate Functions T2 (external count input to Timer/Counter 2),clock-out T2EX (Timer/Counter 2 capture/reload trigger and direction control) MOSI (used for In-System Programming) MISO (used for In-System Programming) SCK (used for In-System Programming) Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses toexternal data memory that use 16-bit ddresses (MOVX

@ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins,they are pulled high by the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special featuresof the ATS52, as shown in the following table.

Port 3 also receives some control signals for Flash programming and verification.

Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RST

Alternate Functions RXD (serial input port) TXD (serial output port) INTO (external interrupt 0) INTO (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature

is enabled. ALE/PROG

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG ) during Flash programming.

In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ- ency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has no effect if the microco- ntroller is in external execution mode. PSEN

Program Store Enable (PSEN ) is the read strobe to external program memory. When the ATS52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA /VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be ternally latched on reset. EA should be strapped to VCC for internal rogram executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming. XTAL1

Input to the inverting oscillator amplifier and input to the nternal clock operating

circuit.

XTAL2

Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or nactive values of the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H , RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. Timer 2 Operating Modes

RCLK+TCLK 0 0 1 × CP/RL2 0 1 × × TR2 1 1 1 0 MODE 16-bit Auto-reload 16-bit Capture Baud Rate Generator (Off) In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high

in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To nsure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

Interrupts

The ATS52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which

disables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the ATS52, bit position IE.5 is also unimplemented.

User software should not write 1s to these bit positions, since they may be used in future AT products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

Reference data:

1. the ATMEL company ATS52 technical manuals

2.Shenzhen Development Co., Ltd. ATC52 Datasheets source SCM

3.Fudan University Press, single-chip microprocessor theory, application and test ZHANG You-de, etc.