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专利名称：INTEGRATED CIRCUIT WTH LOW POWER
SCAN FLIP-FLOP
发明人：Sian Lu,Hao Wang申请号：US14580237申请日：20141223
公开号：US20160091566A1公开日：20160331
专利附图：
摘要：A scan-testable integrated circuit includes first and second flip-flops. The firstflip-flop includes first and second latches and the second flip-flop includes third andfourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop
shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts asecond bit of the test pattern into the second flip-flop. The logic circuit deactivates aclock signal provided to the third latch, which is a master latch, when the logic states ofthe first and second bits are equal. The output terminals of the third and fourth latchesare retained at the logic state corresponding to the first bit, thereby reducing powerconsumption.
申请人：Sian Lu,Hao Wang
地址：Tianjin CN,Tianjin CN
国籍：CN,CN
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