Chapter 5:Example Design
Table 5-6:
0x02780x027C0x0280–0x02AF
Status and Statistics Register Map (Cont’d)
Register Name
STAT_LT_COEFFICIENT1_REGSTAT_AN_LINK_CTL_REG_2Reserved
Address
Histogram/Counter Registers(1)
0x02B00x02B80x02C00x02C80x02D00x02D80x02E00x02E80x02F00x02F80x03000x03080x03100x03180x03200x03280x03300x03380x03400x03480x03500x03580x03600x03680x03700x03780x03800x03880x03900x03980x03A0
TICK_REG
STAT_CYCLE_COUNTSTAT_RX_BIP_ERR_0STAT_RX_BIP_ERR_1STAT_RX_BIP_ERR_2STAT_RX_BIP_ERR_3STAT_RX_BIP_ERR_4STAT_RX_BIP_ERR_5STAT_RX_BIP_ERR_6STAT_RX_BIP_ERR_7STAT_RX_BIP_ERR_8STAT_RX_BIP_ERR_9STAT_RX_BIP_ERR_10STAT_RX_BIP_ERR_11STAT_RX_BIP_ERR_12STAT_RX_BIP_ERR_13STAT_RX_BIP_ERR_14STAT_RX_BIP_ERR_15STAT_RX_BIP_ERR_16STAT_RX_BIP_ERR_17STAT_RX_BIP_ERR_18STAT_RX_BIP_ERR_19STAT_RX_FRAMING_ERR_0STAT_RX_FRAMING_ERR_1STAT_RX_FRAMING_ERR_2STAT_RX_FRAMING_ERR_3STAT_RX_FRAMING_ERR_4STAT_RX_FRAMING_ERR_5STAT_RX_FRAMING_ERR_6STAT_RX_FRAMING_ERR_7STAT_RX_FRAMING_ERR_8
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
Chapter 5:Example Design
Table 5-6:
0x03A80x03B00x03B80x03C00x03C80x03D00x03D80x03E00x03E80x03F00x03F80x0400–0x04100x04180x04200x04280x04300x04380x04400x04480x04500x04580x04600x05000x05080x05100x05180x05200x05280x05300x05380x05400x05480x05500x05580x0560
Status and Statistics Register Map (Cont’d)
Register Name
STAT_RX_FRAMING_ERR_9STAT_RX_FRAMING_ERR_10STAT_RX_FRAMING_ERR_11STAT_RX_FRAMING_ERR_12STAT_RX_FRAMING_ERR_13STAT_RX_FRAMING_ERR_14STAT_RX_FRAMING_ERR_15STAT_RX_FRAMING_ERR_16STAT_RX_FRAMING_ERR_17STAT_RX_FRAMING_ERR_18STAT_RX_FRAMING_ERR_19Reserved
STAT_RX_BAD_CODEReservedReservedReservedReservedReservedReservedReserved
STAT_TX_FRAME_ERRORReserved
STAT_TX_TOTAL_PACKETSSTAT_TX_TOTAL_GOOD_PACKETSSTAT_TX_TOTAL_BYTESSTAT_TX_TOTAL_GOOD_BYTESSTAT_TX_PACKET__BYTESSTAT_TX_PACKET_65_127_BYTESSTAT_TX_PACKET_128_255_BYTESSTAT_TX_PACKET_256_511_BYTESSTAT_TX_PACKET_512_1023_BYTESSTAT_TX_PACKET_1024_1518_BYTESSTAT_TX_PACKET_1519_1522_BYTESSTAT_TX_PACKET_1523_1548_BYTESSTAT_TX_PACKET_1549_2047_BYTES
Address
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
Chapter 5:Example Design
Table 5-6:
0x05680x05700x05780x05800x05880x0590–0x05B00x05B80x05C00x05C80x05D00x05D80x05E00x05E80x05F00x05F80x06000x06080x06100x06180x06200x06280x06300x06380x000x080x06500x06580x06600x06680x06700x06780x06800x06880x06900x0698
Status and Statistics Register Map (Cont’d)
Register Name
STAT_TX_PACKET_2048_4095_BYTESSTAT_TX_PACKET_4096_8191_BYTESSTAT_TX_PACKET_8192_9215_BYTESSTAT_TX_PACKET_LARGESTAT_TX_PACKET_SMALLReserved
STAT_TX_BAD_FCSReservedReserved
STAT_TX_UNICASTSTAT_TX_MULTICASTSTAT_TX_BROADCASTSTAT_TX_VLANSTAT_TX_PAUSESTAT_TX_USER_PAUSEReserved
STAT_RX_TOTAL_PACKETSSTAT_RX_TOTAL_GOOD_PACKETSSTAT_RX_TOTAL_BYTESSTAT_RX_TOTAL_GOOD_BYTESSTAT_RX_PACKET__BYTESSTAT_RX_PACKET_65_127_BYTESSTAT_RX_PACKET_128_255_BYTESSTAT_RX_PACKET_256_511_BYTESSTAT_RX_PACKET_512_1023_BYTESSTAT_RX_PACKET_1024_1518_BYTESSTAT_RX_PACKET_1519_1522_BYTESSTAT_RX_PACKET_1523_1548_BYTESSTAT_RX_PACKET_1549_2047_BYTESSTAT_RX_PACKET_2048_4095_BYTESSTAT_RX_PACKET_4096_8191_BYTESSTAT_RX_PACKET_8192_9215_BYTESSTAT_RX_PACKET_LARGESTAT_RX_PACKET_SMALLSTAT_RX_UNDERSIZE
Address
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
