二进制转格雷码（bin2gary）
先编译再配管脚
5输入：in（0..3）【47..】+EN【59】 cout:out std_logic;
led_com:out std_logic); end;
architecture one of add4b is
signal crlt:std_logic_vector(4 downto 0); 4输出【7..】+共阴极【141】
library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_signed.all; entity bin2gary is port(
data_in:in std_logic_vector(3 downto 0); en:in std_logic;
data_out:out std_logic_vector(3 downto 0); common:out std_logic );
end entity;
architecture bin2gary_arch of bin2gary is begin
data_out(0)<=(data_in(0) xor data_in(1))and en; data_out(1)<=(data_in(1) xor data_in(2))and en; data_out(2)<=(data_in(2) xor data_in(3))and en; data_out(3)<=data_in(3) and en; common<='1';
end bin2gary_arch;
八位加法器（add4b）
图形文件置顶层再编译
16输入a,b【..】
9输出out【7..】+共阴极【141】
library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_signed.all; entity add4b is port(
cin:in std_logic;
a,b:in std_logic_vector(3 downto 0); s:out std_logic_vector(3 downto 0);
signal aa,bb:std_logic_vector(4 downto 0); begin
led_com<='1';
aa<='0'&a(3 downto 0); bb<='0'&b(3 downto 0); crlt<=aa+bb+cin;
s(3 downto 0)<=crlt(3 downto 0); cout<=crlt(4); end one;
计数器（counter10）
2输入：reset【47】+clk【48】
6输出：dout【7..10】+c【11】+led_com【141】
library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter10 is port(clk:in std_logic; reset:in std_logic;
dout:out std_logic_vector(3 downto 0); c:out std_logic;
led_com:out std_logic); end counter10;
architecture behavioral of counter10 is signal count:std_logic_vector(3 downto 0); begin
dout<=count; process(count) begin
if count=\"1001\"then c<='1'; else c<='0'; end if;
end process;
process(clk,reset) begin
if reset='0'then count<=\"0000\"; count<=count+'1'; end if; end if;
end process; led_com<='1'; end behavioral;
elsif rising_edge(clk)then if count=\"1001\"then count<=\"0000\"; else
发光二极管控制（asm_led）
2输入：rst【47】+clk【55】
输出：led_light【20..7】（左到右）+led_com【141】
library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_signed.all;
entity asm_led is port(rst:in std_logic; clk: in std_logic; led_com: out std_logic;
led_light:out std_logic_vector(11 downto 0) );
p2: process(clk) begin if (rst='0')then
count<=(others=>'0');
elsif (clk'event and clk='1')then
if (count = \"100110001001011010000000\")then count<=(others=>'0'); c<='1'; else
count <= count+1; c<='0'; end if; end if;
end asm_led;
architecture a of asm_led is
signal count:std_logic_vector(23 downto 0); signal c:std_logic;
signal q:std_logic_vector(11 downto 0):=\"100000000000\"; begin
led_com<='1'; p1: process(c,q)
begin
if (rst='0')then
q<=\"100000000000\";
elsif (c'event and c='1')then
q(11 downto 0)<=q(0)&q(11 downto 1);
end process; end a;
end if; led_light<=q; end process;
