ADCMP608芯片手册

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Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V,

Single-Supply TTL/CMOS Comparator

Data Sheet

FEATURES

Fully specified rail to rail at VCC = 2.5 V to 5.5 V

Input common-mode voltage from −0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage 40 ns propagation delay Low power: 1 mW at 2.5 V Shutdown pin

Power supply rejection > 60 dB −40°C to +125°C operation

APPLICATIONS

High speed instrumentation

Clock and data signal restoration Logic level shifting or translation High speed line receivers Threshold detection

Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators

Current-/voltage-controlled oscillators

GENERAL DESCRIPTION

The ADCMP608 is a fast comparator fabricated on XFCB2, an Analog Devices, Inc. proprietary process. This comparator is exceptionally versatile and easy to use. Features include an input range from VEE − 0.2 V to VCC + 0.2 V, low noise, TTL-/CMOS-compatible output drivers, and shutdown inputs. The device offers 40 ns propagation delays driving a 15 pF load with 10 mV overdrive on 500 µA typical supply current.

A flexible power supply scheme allows the device to operate with a single +2.5 V positive supply and a −0.2 V to + 2.7 V input signal range up to a +5.5 V positive supply with a −0.2 V to +5.7 V input signal range.

Rev. B

Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADCMP608

FUNCTIONAL BLOCK DIAGRAM

NONINVERTINGINPUT+ADCMP608Q OUTPUTINVERTINGINPUT–100-9S6DN760

Figure 1.

The TTL-/CMOS-compatible output stage is designed to drive up to 15 pF with full rated timing specifications and to degrade in a graceful and linear fashion as additional capacitance is added. The input stage of the comparator offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded.

The ADCMP608 is available in a tiny 6-lead SC70 package with a single-ended output and a shutdown pin.

ADCMP608

Data Sheet

Applications Information .................................................................7 Power/Ground Layout and Bypassing ........................................7 TTL-/CMOS-Compatible Output Stage ....................................7 Optimizing Performance ..............................................................7 Comparator Propagation Delay Dispersion ..................................7 Crossover Bias Point .....................................................................8 Minimum Input Slew Rate Requirement ...................................8 Typical Application Circuits ............................................................9 Outline Dimensions ....................................................................... 10 Ordering Guide .......................................................................... 10

TABLE OF CONTENTS

Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings ............................................................ 4 Thermal Resistance ...................................................................... 4 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 Typical Performance Characteristics ............................................. 6

REVISION HISTORY

11/14—Rev. A to Rev. B

Changes to Figure 7 and Figure 8 ................................................... 6

6/14—Rev. 0 to Rev. A

Changes to Temperature Parameter, Table 2 ................................. 4 Changes to Ordering Guide .......................................................... 10

4/07—Revision 0: Initial Version

Rev. B | Page 2 of 10

Data Sheet SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VCC = 2.5 V, TA = −40°C to +125°C. Typical values are TA = 25°C, unless otherwise noted. Table 1.

Parameter

DC INPUT CHARACTERISTICS Voltage Range

Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance

Resistance, Differential Mode Resistance, Common Mode Active Gain

Common-Mode Rejection SHUTDOWN PIN CHARACTERISTICS1 VIH VIL IIH

Sleep Time Wake-Up Time

DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level AC PERFORMANCE2 Rise Time/Fall Time Propagation Delay

Propagation Delay Skew—Rising to Falling Transition Overdrive Dispersion

Common-Mode Dispersion POWER SUPPLY

Supply Voltage Range Positive Supply Current Power Dissipation

Power Supply Rejection Ratio Shutdown Current

ADCMP608

Symbol VP, VN

Conditions VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V

Min −0.2 −0.2 −5.0 −0.4 −1.0

Typ Max VCC VCC VCC +5.0 +0.4 +1.0 7000 4000

Unit V V V mV µA µA pF kΩ kΩ dB dB dB V V µA ns ns V V ns ns ns ns ns ns ns ns

VOS IP, IN CP, CN

−0.5 V to VCC + 0.5 V −0.5 V to VCC + 0.5 V

AV CMRR

VCC = 2.5 V, VCM = −0.2 V to 2.7 V VCC = 5.5 V

Comparator is operating Shutdown guaranteed VIH = VCC lCC < 100 µA

VPP = 10 mV, output valid VCC = 2.5 V to 5.5 V

IOH = 0.8 mA, VCC = 2.5 V IOL = 0.8 mA, VCC = 2.5 V VCC = 2.5 V to 5.5 V

10% to 90%, VCC = 2.5 V 10% to 90%, VCC = 5.5 V VOD = 10 mV, VCC = 2.5 V VOD = 50 mV, VCC = 5.5 V VCC = 2.5 V VCC = 5.5 V

10 mV < VOD < 125 mV −0.2 V < VCM < VCC + 0.2 V

±3

200 100

45 45 2.0 −0.2 −6

VCC +0.4 +6

+0.4 300 150

tSD tH VOH VOLtR, tF tPD

VCC − 0.4

0.4

25 to 50 45 to 75 30 to 50 35 to 60 4.5 8 12 1.5

2.5

5.5 800 1300 2.0 7.15 350

VCC IVCC PD PSRR ISD

VCC = 2.5 V VCC = 5.5 V VCC = 2.5 V VCC = 5.5 V

VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V

550 800 1.375 4.95

−50

250

V µA µA mW mW dB µA

The output will be in a high impedance mode when the device is in shutdown mode. Note that this feature should be used with care since the enable/disable time is much longer than with a true tristate output. 2

VIN = 100 mV square input at 1 MHz, VCM = 0 V, CL = 15 pF, VCCI = 2.5 V, unless otherwise noted.

Rev. B | Page 3 of 10

ADCMP608

Data Sheet

THERMAL RESISTANCE

ABSOLUTE MAXIMUM RATINGS

Table 2.

θJA is specified for the worst-case conditions, that is, a device Parameter Rating soldered in a circuit board for surface-mount packages. Supply Voltages

Supply Voltage (VCC to GND) −0.5 V to +6.0 V

Table 3. Thermal Resistance

Supply Differential −6.0 V to +6.0 V

Package Type θJA1 Unit Input Voltages

ADCMP608 6-Lead SC70 426 °C/W

Input Voltage −0.5 V to VCC+ 0.5 V 1

Measurement in still air.

Differential Input Voltage ±(VCC + 0.5 V)

Maximum Input/Output Current ±50 mA

ESD CAUTION Shutdown Control Pin

Applied Voltage (SDN to GND) −0.5 V to VCC + 0.5 V Maximum Input/Output Current ±50 mA Output Current ±50 mA

Temperature Operating Temperature, Ambient −40°C to +125°C

Operating Temperature, Junction 150°C

Storage Temperature Range −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Rev. B | Page 4 of 10

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Q16ADCMP608

VCCSDNVN06769-002ADCMP608VEE2VP3TOP VIEW(Not to Scale)54Figure 2. Pin Configuration

Table 4. ADCMP608 Pin Function Descriptions

Pin No. 1 2 3 4 5 6

Mnemonic Description Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the

analog voltage at the inverting input, VN.

VEE Negative Supply Voltage. VP Noninverting Analog Input. VN Inverting Analog Input. SDN Shutdown. Drive this pin low to shut down the device. VCC VCC Supply.

Rev. B | Page 5 of 10

ADCMP608

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VCC =2.5 V, TA = 25°C, unless otherwise noted.

54PROPAGATION DELAY (ns)38.037.837.637.437.237.036.836.636.406769-003321PROPAGATION DELAY FALLIB (µA)0–1–2–3–4–5–1.0+125°C+25°C–40°C–0.500.51.01.52.02.53.0PROPAGATION DELAY RISE36.236.00.51.01.52.02.53.53.0VCM AT VCC (2.5V)VCM AT VCC (2.5V)Figure 3. Input Bias Current vs. Input Common-Mode Voltage Figure 6. Propagation Delay vs. Input Common-Mode Voltage

60555045QTPD (ns)4035302520VCC = 2.5VRISE DELAY050VCC = 5.5VRISE DELAYVCC = 5.5VFALL DELAYVCC = 2.5VFALL DELAY06769-0040.5V/DIV100ns/DIV06769-00706769-008100OD (mV)150

Figure 7. 1 MHz Output Voltage Waveform VCC = 2.5 V

Figure 4. Propagation Delay vs. Input Overdrive at VCC = 2.5 V and 5.5 V

1.5SOURCE1.0SINKLOAD CURRENT (mA)Q0.50–0.506769-005–1.0–1.0–0.51V/DIV100ns/DIV

00.51.01.52.0VOUT (V)2.53.03.54.0Figure 5. Load Current (mA) vs. VOH/VOL Figure 8. 1 MHz Output Voltage Waveform VCC = 5.5 V

Rev. B | Page 6 of 10

06769-006Data Sheet

APPLICATIONS INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCMP608 comparator is a high speed device. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCC) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application.

It is also important to adequately bypass the input and output supplies. A 0.1 μF bypass capacitor should be placed as close as possible to the VCC supply pin. The capacitor should be connected to the GND plane with redundant vias placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies.

A1VLOGICQ1ADCMP608

+IN–INAVOUTPUTA2Q206769-009GAIN STAGEOUTPUT STAGEFigure 9. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, common power and ground

impedances, or other layout issues can severely limit performance and can often cause oscillation. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Higher impedances encourage undesired coupling.

TTL-/CMOS-COMPATIBLE OUTPUT STAGE

Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The output of the ADCMP608 is designed to directly drive one Schottky TTL, or three low power Schottky TTL loads, or the equivalent. For large fan outs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator.

With the rated 15 pF load capacitance applied, more than half of the total device propagation delay is output stage slew time. Because of this, the total propagation delay decreases as VCC decreases, and instability in the power supply may appear as excess delay dispersion.

Delay is measured to the 50% point for whatever supply is in use; thus, the fastest times are observed with the VCC supply at 2.5 V, and larger values are observed when driving loads that switch at other levels.

Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations.

The TTL-/CMOS-compatible output stage is shown in the simplified schematic diagram (see Figure 9). Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads.

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP608 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mV to VCC – 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold).

Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instru-mentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (see Figure 10 and Figure 11).

ADCMP608 dispersion is typically < 12 ns as the overdrive varies from 10 mV to 125 mV. This specification applies to both positive and negative signals because the device has very closely matched delays for both positive-going and negative-going

inputs, and very low output skews. Remember to add the actual device offset to the overdrive for repeatable dispersion measurements.

Rev. B | Page 7 of 10

ADCMP608

500mV OVERDRIVEINPUT VOLTAGE10mV OVERDRIVEVN ± VOSDISPERSION010-9Q OUTPUT6760

Figure 10. Propagation Delay—Overdrive Dispersion

INPUT VOLTAGE1V/nsVN ± VOS10V/nsDISPERSION110-9Q OUTPUT6760

Figure 11. Propagation Delay—Slew Rate Dispersion

Data Sheet

CROSSOVER BIAS POINT

Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some

predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents.

The ADCMP608 slightly elaborates on this scheme. Crossover points can be found at approximately 0.8 V and 1.6 V.

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PC board design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation may be encountered. These oscillations are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and PC board. In many applications, chattering is not harmful.

Rev. B | Page 8 of 10

Data Sheet

ADCMP608

2.5V TO 5V0.1µFCMOSVCC2.5V TO 5VTYPICAL APPLICATION CIRCUITS

INPUT2kΩ2kΩADCMP608OUTPUT06769-012LVDS100ΩADCMP608OUTPUT06769-0130.1µF

Figure 12. Self-Biased, 50% Slicer

Figure 13. LVDS-to-CMOS Receiver

Rev. B | Page 9 of 10

ADCMP608

Data Sheet

2.202.001.80OUTLINE DIMENSIONS

1.351.251.156152432.402.101.801.30BSC1.000.900.700.65BSC0.400.101.100.80COMPLIANTTOJEDECSTANDARDSMO-203-AB072809-A0.10MAXCOPLANARITY0.100.300.15SEATINGPLANE0.220.080.460.360.26

Figure 14. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range ADCMP608BKSZ-R2 −40°C to +125°C ADCMP608BKSZ-RL −40°C to +125°C ADCMP608BKSZ-REEL7 −40°C to +125°C EVAL-ADCMP608BKSZ

Package Description

6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] Evaluation Board

Package

Option KS-6 KS-6 KS-6

Branding G0U G0U G0U

Z = RoHS Compliant Part.

Rev. B | Page 10 of 10

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