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Technique of producing tapered features in integra

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专利名称:Technique of producing tapered features in

integrated circuits

发明人:James P. Roland申请号:US06/442545申请日:19821118公开号:US04514252A公开日:19850430

摘要:A technique is presented for producing tapered walls. In accordance with thedisclosed technique, a mask is generated on a workpiece and the workpiece is etchedthrough the mask to replicate the mask pattern into the mask. These steps result inwalls at the boundaries of the replicated mask features. In many such processes, thesewalls are either substantially vertical or have an overhanging portion of the walls. Inorder to taper the walls, the upper corners of the walls are cut away to remove theoverhang or to cut the corner back an additional amount to produce a controlledamount of taper.

申请人:HEWLETT-PACKARD COMPANY

代理人:John A. Frazzini

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