PRELIMINARY DATA SHEETMICRONASBSP 3505DBasebandSound ProcessorEdition Oct. 21, 19986251-481-1PDMICRONASBSP 3505DContentsPage4444555666799991011111212131314141515161717171718181819191920202020Section1.1.1.1.2.1.3.2.2.1.2.1.1.2.2.2.3.2.4.3.3.1.3.2.3.2.1.3.2.2.3.2.3.3.2.4.3.3.4.4.1.4.2.4.3.4.4.4.4.1.4.4.2.4.4.3.4.4.4.4.4.5.4.4.6.4.4.7.4.4.8.4.4.9.4.4.10.4.4.11.4.4.12.4.4.13.4.4.14.4.5.4.5.1.4.5.2.4.5.3.4.5.4.4.5.5.TitleIntroductionBSP 3505D Integrated FunctionsFeatures of the DSP-SectionFeatures of the Analog SectionArchitecture of the BSP 3505DAnalog Section and SCART Switching FacilitiesStandby ModeBSP 3505DAudio Baseband ProcessingClock and Crystal SpecificationsDigital Control Output PinsI2C Bus Interface: Device and SubaddressesProtocol DescriptionProposal for BSP 3505D I2C TelegramsSymbolsWrite TelegramsRead TelegramsExamplesStart Up Sequence: Power Up and I2C-ControllingProgramming the BSP 3505DRegister ‘MODE_REG’DSP Write Registers: Table and AddressesDSP Read Registers: Table and AddressesDSP Write Registers: Functions and ValuesVolume Loudspeaker ChannelBalance Loudspeaker ChannelBass Loudspeaker ChannelTreble Loudspeaker ChannelLoudness Loudspeaker ChannelSpatial Effects Loudspeaker ChannelVolume SCART1Channel Source ModesChannel Matrix ModesSCART PrescaleDefinition of Digital Control Output PinsDefinition of SCART-Switching FacilitiesBeeperAutomatic Volume Correction (AVC)DSP Read Registers: Functions and ValuesQuasi-Peak DetectorBSP Hardware Version CodeBSP Major Revision CodeBSP Product CodeBSP ROM Version CodePRELIMINARY DATA SHEET2MicronasPRELIMINARY DATA SHEETBSP 3505DContents, continuedPage212123263031313234374040Section5.5.1.5.2.5.3.5.4.5.5.5.5.1.5.5.2.5.5.3.6.7.8.TitleSpecificationsOutline DimensionsPin Connections and Short DescriptionsPin ConfigurationsPin CircuitsElectrical CharacteristicsAbsolute Maximum RatingsRecommended Operating ConditionsCharacteristicsApplication CircuitAppendix A: BSP 3505D Version HistoryData Sheet HistoryMicronas3BSP 3505DBaseband Sound ProcessorRelease Notes: The hardware description in thisdocument is valid for the BSP 3505D version A2.1. IntroductionThe BSP 3505D is designed as a single-chip BasebandSound Processor for applications in analog and digitalTV sets, video recorders, and satellite receivers.The IC is produced in submicron CMOS technology, andis fully pin and software compatible to the MSP 34xxfamily. The BSP 3505D is available in a PLCC68,PSDIP, PSDIP52, PQFP80, and in a PQFP44 pack-age.Note: The BSP 3505D version has reduced control reg-isters and less functional pins. The remaining registersare software compatible to the MSP 34xxD. The pinningis compatible to the MSP 34xxD.1.1. BSP 3505D Integrated Functions–Stereo baseband input via integrated A/D converters–Two stereo D/A converters–AVC: Automatic Volume Correction–Bass, treble, volume, loudness processing–Full SCART in/out matrix without restrictions–spatial effect (pseudostereo / basewidth enlargement)–Digital control output pins D_CTR_OUT0/1–Reduction of necessary controlling–Less external componentsMONO INSCART1 INSCART2 IN22PRELIMINARY DATA SHEET1.2. Features of the DSP-Section–flexible selection of audio sources to be processed–digital baseband processing: volume, bass, treble,loudness, and spatial effects–simple controlling of volume, bass, treble, loudness,and spatial effects1.3. Features of the Analog Section–two selectable analog stereo audio baseband inputs(= two SCART inputs)input level: ≤2 V RMS, input impedance: ≥25 kΩ–one selectable analog mono input: input level: ≤2 V RMS, input impedance: ≥15 kΩ–stereo high-quality A/D converter, S/N-Ratio: ≥85 dB–20 Hz to 20 kHz bandwidth for SCART-to-SCART-copy facilities–loudspeaker: stereo four-fold oversampled D/A-con-verteroutput level per channel: max. 1.4 VRMSoutput resistance: max. 5 kΩS/N-ratio: ≥85 dB at maximum volumemax. noise voltage in mute mode: ≤10 µV (BW: 20 Hz ...16 kHz)–stereo four-fold oversampled D/A converter supplyinga stereo SCART-output output level per channel: max. 2 V RMS, output resistance: max. 0.5 kΩ, S/N-Ratio: ≥85 dB (20 Hz...16 kHz)2I2C2LoudspeakerOUTBSP 3505D2SCARTOUTFig. 1–2: Main I/O Signals BSP 3505DTunerSIFVIFFM/AM MonoLoudspeakerSCARTInputsSCART1SCART22BSP 3505D2SCART1SCARTOutput2Fig. 1–1: Typical BSP 3505D application4MicronasPRELIMINARY DATA SHEETBSP 3505DSCART_INSC1_IN_L/R2. Architecture of the BSP 3505DFig. 2–2 shows a simplified block diagram of the IC. Itsarchitecture is split into two main functional blocks:1.DSP (digital signal processing) section performingaudio baseband processing2.analog section containing two A/D-converters,four D/A-converters, and SCART-switching facilities.2.1. Analog Section and SCART Switching FacilitiesThe analog input and output sections include full matrixswitching facilities, which are shown in Fig. 2–1.The switches are controlled by the ACB bits defined inthe audio processing interface (see section 4. Program-ming the BSP 3505D).2.1.1. Standby ModeIf the BSP 3505D is switched off by first pulling STAND-BYQ low, and then disconnecting the 5 V, but keepingthe 8 V power supply (‘Standby’-mode), the switchesS1 and S2 (see Fig. 2–1) maintain their position andfunction. This facilitates the copying from selectedSCART-inputs to SCART-output in the TV-set’s standbymode.In case of power-on start or starting from standby, the ICswitches automatically to the default configuration,shown in Fig. 2–1. This action takes place after the firstI2C transmission into the DSP part. By transmitting theACB register first, the individual default setting mode ofthe TV set can be defined.SC2_IN_L/Rto Audio BasebandProcessing (DSP_IN)ADSCARTL/RMONO_INS1intern. Sig-nal LinesPinsSCART_OUTfrom Audio BasebandProcessing (DSP_OUT)SCART1_L/RDASC1_OUT_L/RS2Fig. 2–1: SCART-Switching Facilities (see 4.4.12.)positions show the default configuration after PowerOn Reset. Note: SCART_OUT is undefined after RESET!XTAL_INXTAL_OUTClockDSPLOUD-SPEAKER LLOUD-SPEAKER RD_CTR_OUT0/1D/AD/ADACM_LLoudspeakerDACM_RMonoMONO_INSC1_IN_LSCART1SC1_IN_RA/DA/DSCARTLSCARTRSCART1_LSCART1_RD/AD/ASC1_OUT_LSCARTSC1_OUT_RSC2_IN_LSCART2SC2_IN_RSCART Switching FacilitiesFig. 2–2: Architecture of the BSP 3505DMicronas5BSP 3505D2.2. BSP 3505D Audio Baseband ProcessingAll audio baseband functions are performed by digitalsignal processing (DSP). The DSP functions aregrouped into three processing parts: input preproces-sing, channel source selection, and channel postpro-cessing (see Fig. 2–3).The input preprocessing is intended to form a standard-ized signal level.All input and output signals can be processed simulta-neously.2.3. Clock and Crystal SpecificationsRemark on using the crystal: External capacitors ateach crystal pin to ground are required. The higher thecapacitors, the lower the clock frequency results.The nominal free running frequency should match thecenter of the tolerance range between 18.433 and18.431 MHz as closely as possible.2.4. Digital Control Output PinsThe static level of two output pins of the BSP 3505D(D_CTR_OUT0/1) is switchable between HIGH andLOW by means of the I2C-bus. This enables the control-ling of external hardware controlled switches or otherdevices via I2C-bus (see section 4.4.11.)PRELIMINARY DATA SHEETAnalogInputsSCARTLSCARTRSCARTPrescaleLoudspeakerChannelMatrixAVCBassTrebleȍVolumeLoudnessBalanceLoudspeaker LLoudspeaker RLoudspeakerOutputsChannel Souce SelectBeeperSCART1 ChannelMatrixVolumeSCART1_LSCART1_RSCARTOutputQuasi-PeakDetectorSCARTInternal signal lines (see Fig. 2–1)Quasi peak readout LQuasi peak readout RFig. 2–3: Audio Baseband Processing (DSP-Firmware)6MicronasPRELIMINARY DATA SHEETBSP 3505DDue to the internal architecture of the BSP 3505D the ICcannot react immediately to an I2C request. The typicalresponse time is about 0.3 ms for the DSP processorpart. If the receiver (BSP) can’t receive another com-plete byte of data until it has performed some other func-tion; for example, servicing an internal interrupt, it canhold the clock line I2C_CL LOW to force the transmitterinto a wait state. The positions within a transmissionwhere this may happen are indicated by ’Wait’ in section3.1. The maximum Wait-period of the BSP during normaloperation mode is less than 1 ms.I2C-Bus conditions caused by BSP hardware problems:In case of any internal error, the BSPs wait-period is ex-tended to 1.8 ms. Afterwards, the BSP does not ac-knowledge (NAK) the device address. The data line willbe left HIGH by the BSP and the clock line will be re-leased. The master can then generate a STOP conditionto abort the transfer.By means of NAK, the master is able to recognize the er-ror state and to reset the IC via I2C-Bus. While transmit-ting the reset protocol (s. 5.2.4.) to ‘CONTROL’, themaster must ignore the not acknowledge bits (NAK) ofthe BSP.A general timing diagram of the I2C Bus is shown inFig. 3–2.3. I2C Bus Interface: Device and SubaddressesAs a slave receiver, the BSP 3505D can be controlled viaI2C bus. Access to internal memory locations isachieved by subaddressing. The DSP processor parthas its own subaddressing register bank.In order to allow for more BSP or MSP ICs to be con-nected to the control bus, an ADR_SEL pin has been im-plemented. With ADR_SEL pulled to high, low, or leftopen, the BSP 3505D responds to changed device ad-dresses. Thus, three identical devices can be selected.By means of the RESET bit in the CONTROL register,all devices with the same device address are reset.The IC is selected by asserting a special device addressin the address part of an I2C transmission. A device ad-dress pair is defined as a write address (80, 84, or 88hex)and a read address (81, 85, or hex). Writing is done bysending the device write address first, followed by thesubaddress byte, two address bytes, and two data by-tes. Reading is done by sending the device write ad-dress, followed by the subaddress byte and two addressbytes. Without sending a stop condition, reading of theaddressed data is completed by sending the device readaddress (81, 85, or hex) and reading two bytes of data.Refer to Fig. 3–1: I2C Bus Protocol and section 3.2. Pro-posal for BSP 3505D I2C Telegrams.Table 3–1: I2C Bus Device AddressesADR_SELModeBSP device addressWrite80hexLowRead81hexWrite84hexHighRead85hexWrite88hexLeft OpenReadhexTable 3–2: I2C Bus SubaddressesNameCONTROLTESTWR_DSPRD_DSPBinary Value0000 00000000 00010001 00100001 0011Hex Value00011213ModeWriteWriteWriteWriteFunctionsoftware resetonly for internal usewrite address DSPread address DSPMicronas7BSP 3505DTable 3–3: Control Register (Subaddress: 00hex)NameCONTROLSubaddress00hexMSB1 : RESET0 : normal14013..10PRELIMINARY DATA SHEETLSB03.1. Protocol DescriptionWrite to DSPSwritedeviceaddressWaitACKsub-addrACKaddr-bytehighACKaddr-byte lowACKdata-byte highACKdata-byte lowACKPRead from DSPSwritedeviceaddressWaitACKsub-addrACKaddr-bytehighACKaddr-bytelowACKSreaddeviceaddressWaitACKdata-bytehighACKdata-bytelowNAKPWrite to Control or Test RegistersSwritedeviceaddressWaitACKsub-addrACKdata-byte highACKdata-byte lowACKPNote:S = I2C-Bus Start Condition from masterP = I2C-Bus Stop Condition from masterACK = Acknowledge-Bit: LOW on I2C_DA from slave (=BSP, gray) or master (=CCU, hatched)NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (=CCU, hatched) to indicate ‘End of Read’or from BSP indicating internal error stateWait = I2C-Clock line held low by the slave (=BSP) while interrupt is serviced (<1.8 ms)I2C_DASI2C_CLFig. 3–1: I2C bus protocol(Data: MSB first)10P(MSB first; data must be stable while clock is high)8MicronasPRELIMINARY DATA SHEETBSP 3505DFI2CI2C_CLTI2C4TI2C3TI2C1I2C_DA as inputTI2C5TI2C6TI2C2TI2COL2I2C_DA as outputTI2COL1Fig. 3–2: I2C bus timing diagram3.2. Proposal for BSP 3505D I2C Telegrams3.2.1. Symbolsdawdar<>aaddwrite device addressread device addressStart ConditionStop ConditionAddress ByteData Byte3.2.2. Write Telegramswrite to CONTROL registerwrite data into DSP3.2.3. Read Telegrams read data from DSP3.2.4. Examples<80 00 80 00><80 00 00 00><80 12 00 08 02 20>RESET BSP staticallyclear RESETset loudspeaker channel sourceto SCART, stereoMicronas9BSP 3505D3.3. Start Up Sequence: Power Up and I2C-ControllingAfter power on or RESET (see Fig. 3–3), the IC is in aninactive state. The CCU has to transmit the required co-efficient set for a given operation via the I2C bus. Initial-ization must start with the MODE Register.The reset pin should not be >0.45*DVSUP (see recom-mended conditions) before the 5 Volt digital power sup-ply (DVSUP) and the analog power supply (AVSUP) are>4.75 Volt AND the BSP clock is running. (Delay: 0.5 mstyp, 2 ms max)This means, if the reset low–high edge starts with adelay of 2 ms after DVSUP and AVSUP >4,75 Volt, evenunder worst case conditions, the reset is ok.PRELIMINARY DATA SHEETDVSUP/VAVSUP/V4.75Oscillatortime / msmax. 2RESETQ0.45 * DVSUPtime / msmin. 2time / msFig. 3–3: Power-up sequenceNote: The reset shouldnot reach high level be-fore the oscillator hasstarted. This requires areset delay of >2 ms10MicronasPRELIMINARY DATA SHEETBSP 3505D4. Programming the BSP 3505D4.1. Register ‘MODE_REG’The register ‘MODE_REG’ contains the control bits de-termining the operation mode of the BSP 3505D; Table 4–1 explains all bit positions.Table 4–1: Control word ‘MODE_REG’: All bits are “0” after power-on-resetRegisterMODE_REGBit[0][1][2][3–4][5][6–9][10–15]ProtocollongFunctionnot usedDCTR_TRInot usednot usednot usednot usednot usedDigital_Control_Output tristateWrite Address (hex)0083CommentFunctionmode registerDefinitionmust be 00 : active1 : tristatemust be 1must be 0must be 1must be 0must be 0Micronas11BSP 3505D4.2. DSP Write Registers: Table and AddressesPRELIMINARY DATA SHEETTable 4–2: DSP Write Registers; Subaddress: 12hex; if necessary these registers are readable as well.DSP Write RegisterVolume loudspeaker channelVolume / Clipping Mode loudspeakerBalance loudspeaker channel [L/R]Balance Mode loudspeakerBass loudspeaker channelTreble loudspeaker channelLoudness loudspeaker channelLoudness Filter CharacteristicSpatial effect strength loudspeaker ch.Spatial effect mode/customizeVolume SCART1 channelVolume / Mode SCART1 channelLoudspeaker channel sourceLoudspeaker channel matrixSCART1 channel sourceSCART1 channel matrixQuasi-peak detector sourceQuasi-peak detector matrixPrescale SCARTACB Register (SCART SwitchingFacilities)BeeperAutomatic Volume Correction000Dhex0013hex0014hex0029hex000Chex000Ahex0008hex0007hex0005hex0002hex0003hex0004hex0001hexAddress0000hexHigh/LowHLHLHHHLHLHLHLHLHLHH/LH/LHAdjustable Range, Operational Modes[+12 dB ... –114 dB, MUTE]1/8 dB Steps / Reduce Vol., Tone, Comprom.[0..100 / 100 % and vv][–127..0 / 0 dB and vv][Linear mode / logarithmic mode][+12 dB ... –12 dB][+12 dB ... –12 dB][0 dB ... +17 dB][NORMAL, SUPER_BASS][–100%...OFF...+100%][SBE, SBE+PSE][00hex ... 7Fhex],[+12 dB ... –114 dB, MUTE][Linear mode / logarithmic mode][SCART][SOUNDA, SOUNDB, STEREO, MONO][SCART][SOUNDA, SOUNDB, STEREO, MONO][SCART]Reset ModeMUTE00hex100%/100%linear mode0 dB0 dB0 dBNORMALOFFSBE+PSE00hexlinear modeFM/AMSOUNDAFM/AMSOUNDAFM/AM[SOUNDA, SOUNDB, STEREO, MONO][00hex ... 7Fhex]Bits [15..0][00hex ... 7Fhex]/[00hex ... 7Fhex][off, on, decay time]SOUNDA00hex00hex0/0off4.3. DSP Read Registers: Table and AddressesTable 4–3: DSP Read Registers; Subaddress: 13hexDSP Read RegisterQuasi peak readout leftQuasi peak readout rightAddress0019hex001AhexHigh/LowH&LH&LOutput Range[00hex ... 7FFFhex][00hex ... 7FFFhex]16 bit two’s complement16 bit two’s complement12MicronasPRELIMINARY DATA SHEETBSP 3505DThe BSP 3505D loudspeaker volume function is dividedup in a digital and an analog section.With Fast Mute, volume is reduced to mute position bydigital volume only. Analog volume is not changed. Thisreduces any audible DC plops. Going back from FastMute should be done to the volume step before FastMute was activated.4.4. DSP Write Registers: Functions and ValuesWrite registers are 16 bit wide, whereby the MSB is de-noted bit [15]. Transmissions via I2C bus have to takeplace in 16-bit words. Some of the defined 16-bit wordsare divided into low [7..0] and high [15..8] byte, or in another manner, thus holding two different control entities.All write registers are readable. Unused parts of the16-bit registers must be zero. Addresses not given in thistable must not be written at any time!4.4.1. Volume Loudspeaker ChannelVolume Loudspeaker+12 dB+11.875 dB+0.125 dB0 dB–0.125 dB–113.875 dB–114 dBMuteFast Mute0000hex011111110000011111101110[15..4]Clipping Mode LoudspeakerReduce VolumeReduce Tone Control7F0hex7EEhexCompromise Mode0000hex0000RESET00010010[3..0]0hex1hex2hex011100110010732hex011100110000730hex01110010111072Ehex000000010010012hex000000010000010hex000000000000000hexRESET111111111110FFEhexIf the clipping mode is set to “Reduce Volume”, the fol-lowing clipping procedure is used: To prevent severeclipping effects with bass or treble boosts, the internalvolume is automatically limited to a level where, in com-bination with either bass or treble setting, the amplifica-tion does not exceed 12 dB.If the clipping mode is “Reduce Tone Control”, the bassor treble value is reduced if amplification exceeds 12 dB.If the clipping mode is “Compromise Mode”, the bass ortreble value and volume are reduced half and half if am-plification exceeds 12 dB.The highest given positive 8-bit number (7Fhex) yields ina maximum possible gain of 12 dB. Decreasing the vol-ume register by 1 LSB decreases the volume by 1 dB.Volume settings lower than the given minimum mute theoutput. With large scale input signals, positive volumesettings may lead to signal clipping.Example:Red. VolumeRed. Tone Con.CompromiseVol.:+6 dB3.5Bass:+9 dB967.5Treble:+5 dB555Micronas13BSP 3505D4.4.2. Balance Loudspeaker ChannelPositive balance settings reduce the left channel withoutaffecting the right channel; negative settings reduce theright channel leaving the left channel unaffected. In lin-ear mode, a step by 1 LSB decreases or increases thebalance by about 0.8% (exact figure: 100/127). In loga-rithmic mode, a step by 1 LSB decreases or increasesthe balance by 1 dB.PRELIMINARY DATA SHEET4.4.3. Bass Loudspeaker ChannelBass Loudspeaker+20 dB+18 dB+16 dB+14 dB0002hex011111110111100001110000011010000110000001011000000010000000000100000000RESET11111111111110001010100010100000H7Fhex78hex70hex68hex60hex58hex08hex01hex00hexFFhexF8hexA8hexA0hexBalance Mode Loudspeakerlinearlogarithmic0001hex0000RESET0001[3..0]0hex1hex+12 dB+11 dB+1 dB+1/8 dB0 dBLinear ModeBalance LoudspeakerChannel [L/R]Left muted, Right 100%Left 0.8%, Right 100%Left 99.2%, Right 100%Left 100%, Right 100%Left 100%, Right 99.2%Left 100%, Right 0.8%Left 100%, Right muted0001hex01111111011111100000000100000000RESET111111111000001010000001H–1/8 dB–1 dB7Fhex7Ehex01hex00hexFFhex82hex81hex–11 dB–12 dBWith positive bass settings, internal overflow may occureven with overall volume less than 0 dB. This will lead toa clipped output signal. Therefore, it is not recom-mended to set bass to a value that, in conjunction withvolume, would result in an overall positive gain.Logarithmic ModeBalance LoudspeakerChannel [L/R]Left –127 dB, Right 0 dBLeft –126 dB, Right 0 dBLeft –1 dB, Right 0 dBLeft 0 dB, Right 0 dBLeft 0 dB, Right –1 dBLeft 0 dB, Right –127 dBLeft 0 dB, Right –128 dB0001hex01111111011111100000000100000000RESET111111111000000110000000H7Fhex7Ehex01hex00hexFFhex81hex80hex14MicronasPRELIMINARY DATA SHEETBSP 3505D4.4.5. Loudness Loudspeaker ChannelH78hex70hex08hex01hex00hexFFhexF8hexA8hexA0hexMode Loudness LoudspeakerNormal (constantvolume at 1 kHz)Super Bass (constantvolume at 2 kHz)0004hex00000000RESET00000100L00hex04hexLoudness Loudspeaker+17 dB+16 dB+1 dB0 dB0004hex01000100010000000000010000000000RESETH44hex40hex04hex00hex4.4.4. Treble Loudspeaker ChannelTreble Loudspeaker+15 dB+14 dB+1 dB+1/8 dB0 dB–1/8 dB–1 dB–11 dB–12 dB0003hex0111100001110000000010000000000100000000RESET11111111111110001010100010100000With positive treble settings, internal overflow may occureven with overall volume less than 0 dB. This will lead toa clipped output signal. Therefore, it is not recom-mended to set treble to a value that, in conjunction withvolume, would result in an overall positive gain.Loudness increases the volume of low and high frequen-cy signals, while keeping the amplitude of the 1 kHz ref-erence frequency constant. The intended loudness hasto be set according to the actual volume setting. Be-cause loudness introduces gain, it is not recommendedto set loudness to a value that, in conjunction with vol-ume, would result in an overall positive gain.By means of ‘Mode Loudness’, the corner frequency forbass amplification can be set to two different values. InSuper Bass mode, the corner frequency is shifted up.The point of constant volume is shifted from 1 kHz to2 kHz.Micronas15BSP 3505D4.4.6. Spatial Effects Loudspeaker ChannelSpatial Effect StrengthLoudspeakerEnlargement 100%Enlargement 50%Enlargement 1.5%Effect offReduction 1.5%Reduction 50%Reduction 100%0005hex01111111001111110000000100000000RESET111111111100000010000000H7Fhex3Fhex01hex00hexFFhexC0hex80hexPRELIMINARY DATA SHEETThere are several spatial effect modes available:Mode A (low byte = 00hex) is compatible to the formerlyused spatial effect. Here, the kind of spatial effect de-pends on the source mode. If the incoming signal is inmono mode, Pseudo Stereo Effect is active; for stereosignals, Pseudo Stereo Effect and Stereo BasewidthEnlargement is effective. The strength of the effect iscontrollable by the upper byte. A negative value reducesthe stereo image. A rather strong spatial effect is recom-mended for small TV sets where loudspeaker spacing israther close. For large screen TV sets, a more moderatespatial effect is recommended. In mode A, even in caseof stereo input signals, Pseudo Stereo Effect is active,which reduces the center image.In Mode B, only Stereo Basewidth Enlargement is effec-tive. For mono input signals, the Pseudo Stereo Effecthas to be switched on.It is worth mentioning, that all spatial effects affect ampli-tude and phase response. With the lower 4 bits, the fre-quency response can be customized. A value of 0000binyields a flat response for center signals (L = R) but a highpass function of L or R only signals. A value of 0110binhas a flat response for L or R only signals but a lowpassfunction for center signals. By using 1000bin, the fre-quency response is automatically adapted to the soundmaterial by choosing an optimal high pass gain.Spatial Effect ModeLoudspeakerStereo Basewidth En-largement (SBE) andPseudo Stereo Effect(PSE). (Mode A)Stereo Basewidth En-largement (SBE) only.(Mode B)0005hex0000RESET00000010[7..4]0hex0hex2hexSpatial Effect Cus-tomize CoefficientLoudspeakermax high pass gain2/3 high pass gain1/3 high pass gainmin high pass gainautomatic0005hex[3..0]0000RESET00100100011010000hex2hex4hex6hex8hex16MicronasPRELIMINARY DATA SHEETBSP 3505D4.4.8. Channel Source Modes0007hex0000RESET0001[3..0]0hex1hexLoudspeaker SourceSCART1 SourceQuasi-Peak Detector SourceNONE (MSP3410: FM)0008hex000Ahex000Chex00000000RESET0000000100000010HHH00hex01hex02hex4.4.7. Volume SCART1Volume Mode SCART1linearlogarithmicLinear ModeVolume SCART1OFF0 dB gain (digital full scale (FS)to 2 VRMS output)+6 dB gain (–6 dBFSto 2 VRMS output)0007hex0000 0000RESET0100 0000H00hex40hexNONE (MSP3410: NICAM)SCART4.4.9. Channel Matrix ModesLoudspeaker Matrix0008hex000Ahex000Chex00000000RESET000100000010000000110000LLL00hex10hex20hex30hex0111 11117FhexSCART1 MatrixQuasi-Peak Detector MatrixSOUNDA / LEFTLogarithmic ModeVolume SCART1+12 dB+11.875 dB+0.125 dB0 dB–0.125 dB–113.875 dB–114 dBMute0007hex011111110000011111101110[15..4]7F0hex7EEhexSOUNDB / RIGHTSTEREOMONO011100110010732hex011100110000730hex01110010111072Ehex4.4.10. SCART PrescaleVolume PrescaleSCARTOFF0 dB gain (2 VRMS in-put to digital full scale)+14 dB gain(400mVRMS input todigital full scale)000Dhex0000 0000RESET0001 10010111 1111H00hex19hex7Fhex000000010010012hex000000010000010hex000000000000000hexRESETMicronas17BSP 3505D4.4.11. Definition of Digital Control Output PinsACB RegisterD_CTR_OUT0low (RESET)highD_CTR_OUT1low (RESET)high0013hexx0x10x1x [15..14]4.4.13. BeeperBeeper VolumeOFFPRELIMINARY DATA SHEET0014hex00000000RESET011111110014hex000000010100000011111111H00hex7FhexL01hex40hexFFhexMaximum Volume (fulldigital scale FDS)Beeper Frequency16 Hz (lowest)4.4.12. Definition of SCART-Switching FacilitiesACB RegisterDSP IN Selection of Source:*SC1_IN_L/R MONO_INSC2_IN_L/RMuteSC1_OUT_L/RSelection of Source:SC2_IN_L/RMONO_INSCART1 via D/ASC1_IN_L/RMute0013hex [13..0]1 kHz4 kHz (highest)xx xx00 xx00 0000 xxxx01 xx00 0000xxxx10 xx00 0000xxxx11 xx10 0000A squarewave beeper can be added to the loudspeakerchannel. The addition point is just before volume adjust-ment.xxxxxxxxxx01xx x0x0 000010xx x0x0 000011xx x0x0 000001xx x1x0 000011xx x1x0 0000* = RESET position, which becomes active at thetime of the first write transmission on the controlbus to the audio processing part (DSP). By writingto the ACB register first, the RESET state can beredefined.Note: After RESET, SC1_OUT_L/R is undefined!Note: If “MONO_IN” is selected at the DSP_IN selec-tion, the channel matrix mode of the corresponding out-put channel(s) must be set to “sound A”.18MicronasPRELIMINARY DATA SHEETBSP 3505DTo reset the internal variables, the AVC should beswitched off and on during any channel or sourcechange. For standard applications, the recommendeddecay time is 4 sec.Note: AVC should not be used in any Dolby Prologicmode, except PANORAMA, where no other than theloudspeaker output is active.4.5. DSP Read Registers: Functions and ValuesAll readable registers are 16-bit wide. Transmissions viaI2C bus have to take place in 16-bit words. Single dataentries are 8 bit. Some of the defined 16-bit words aredivided into low and high byte, thus holding two differentcontrol entities.These registers are not writeable.4.5.1. Quasi-Peak DetectorQuasi-Peak Readout LeftQuasi-Peak Readout RightQuasi peak readout0019hex001AhexH+LH+L4.4.14. Automatic Volume Correction (AVC)AVC on/offAVCAVCAVC8 sec4 sec2 sec20 msoff and Reset of int. variablesonDecay Time(long)(middle)(short)(very short)0029hex0000RESET10000029hex1000010000100001[15.12]0hex8hex[11..8]8hex4hex2hex1hexDifferent sound sources fairly often do not have thesame volume level. Advertisement during movies, aswell, usually has a different (higher) volume level thanthe movie itself. The Automatic Volume Correction(AVC) solves this problem and equalizes the volume lev-els.The absolute value of the incoming signal is fed into afilter with 16 ms attack time and selectable decay time.The decay time must be adjusted as shown in the tableabove. This attack/decay filter block works similar to apeak hold function. The volume correction value with itsquasi continuous step width is calculated using the at-tack/decay filter output.The Automatic Volume Correction works with an internalreference level of –18 dBFS. This means, input signalswith a volume level of –18 dBFS will not be affected bythe AVC. If the input signals vary in a range of –24 dB to0 dB, the AVC compensates this.Example: A static input signal of 1 kHz on Scart has anoutput level as shown in the table below.Scart Input0 dbr = 2 Vrms0 dBr–6 dBr–12 dBr–18 dBr–24 dBr–30 dBrVolumeCorrec-tion–18 dB–12 dB–6 dB–0 dB+ 6 dB+ 6 dBMain Output0 dBr = 1.4 Vrms–18 dBr–18 dBr–18 dBr–18 dBr–18 dBr–24 dBr[0hex ... 7FFFhex]values are 16 bit two’scomplementThe quasi peak readout register can be used to read outthe quasi peak level of any input source, in order to ad-just all inputs to the same normal listening level. The re-fresh rate is 32 kHz. The feature is based on a filter timeconstant:attack-time:1.3 msdecay-time:37 msLoudspeaker Volume = 73hex = 0 dBFSScart Prescale = 20hex i.e. 2.0 Vrms = 0 dBFSMicronas19BSP 3505D4.5.2. BSP Hardware Version CodeHardware VersionHardware VersionBSP 3505D – A2001Ehex[00hex ... FFhex]01hexHPRELIMINARY DATA SHEETA change in the hardware version code defines hard-ware optimizations that may have influence on the chip’sbehavior. The readout of this register is identical to thehardware version code in the chip’s imprint.4.5.3. BSP Major Revision CodeMajor RevisionBSP 3505D001Ehex04hexL4.5.4. BSP Product CodeProductBSP 3505D001Fhex05hexH4.5.5. BSP ROM Version CodeROM VersionMajor software revisionBSP 3505D – A2001Fhex[00hex ... FFhex]02hexLA change in the ROM version code defines internal soft-ware optimizations, that may have influence on thechip’s behavior, e.g. new features may have been in-cluded. While a software change is intended to create nocompatibility problems, customers that want to use thenew functions can identify new BSP 3505D versions ac-cording to this number.20MicronasPRELIMINARY DATA SHEETBSP 3505D5. Specifications5.1. Outline Dimensions1.1x 45°91610.4816 x 1.27±0.1= 20.32±0.11.27±0.11.2 x 45°0.91021.6925.125±0.125601.27±0.11524.22±0.127260.4±0.24±0.115.6±0.114±0.10.33.2±0.20.240.27±0.060°...15°20.71190.22±0.07262725.125±0.12543441.94.054.75±0.150.1Fig. 5–1: 68-Pin Plastic Leaded Chip Carrier Package(PLCC68)Weight approximately 4.8 gDimensions in mmSPGS7004-3/5ESPGS0016-4/3ESPGS0015-1/2E2.533521323.8±0.13157.7±0.1(1)19.3±0.118±0.10.347±0.13.2±0.44.8±0.41.90.27±0.061.778±0.050.4570.31±0.120.1±0.51.778±0.051±0.10.45725 x 1.778 = 44.47±0.11.2931 x 1.778 = 55.118±0.1Fig. 5–2: -Pin Plastic Shrink Dual Inline Package(PSDIP)Weight approximately 9.0 gDimensions in mmFig. 5–3: 52-Pin Plastic Shrink Dual In Line Package(PSDIP52)Weight approximately 5.5 gDimensions in mmMicronas16 x 1.27±0.1= 20.32±0.123.424.22±0.121BSP 3505DPRELIMINARY DATA SHEET23 x 0.8 = 18.40.17±0.03651.817.210.39.880123.23±0.21625241.282.700.120814414015 x 0.8 = 12.01.880.80.85Fig. 5–4: 80-Pin Plastic Quad Flat Package(PQFP80)Weight approximately 1.6 gDimensions in mmSPGS0025-1/1E10 x 0.8 = 80.18333413.2232210 x 0.8 = 83.00.3751.3100.8100.81.754411.7513.211122.02.150.1Fig. 5–5: 44-Pin Plastic Quad Flat Package(PQFP44) Weight approx. 0.4 gDimensions in mmSPGS0006-1/1E22MicronasPRELIMINARY DATA SHEETBSP 3505D5.2. Pin Connections and Short DescriptionsNC = not connected; leave vacantLV = if not used, leave vacantDVSS: if not used, connect to DVSSPin No.PLCC68-pin12345671011121314151617181920212223242526–––PSDIP-pin16–15141312111098765432–163626160595857–––PSDIP52-pin14–13121110987–6543–––2152515049484746–––PQFP80-pin9–87654321807978777675–7473727170696867666563PQFP44-pin–––171615141312–111098––––7654–321–––TPNCTPTPTPTPTPI2C_DAI2C_CLNCSTANDBYQADR_SELD_CTR_OUT0D_CTR_OUT1NCNCNCNCTPXTAL_OUTXTAL_INTESTENNCTPTPAVSUPAVSUPNCNCININOUTININININOUTOUTOUTINOUTIN/OUTIN/OUTIN/OUTIN/OUTOUTPin NameX = obligatory; connect as described in circuit diagramAHVSS: connect to AHVSSTypeConnection(ifnotsed)(if not used)Short DescriptionLVLVLVLVLVLVLVXXLVXXLVLVLVLVLVLVLVXXXLVLVLVXXLVLVTest pinNot connectedTest pinTest pinTest pinTest pinTest pinI2C dataI2C clockNot connectedStandby (low-active)I2C Bus address selectDigital control output 0Digital control output 1Not connectedNot connectedNot connectedNot connectedTest pinCrystal oscillatorCrystal oscillatorTest pinNot connectedTest pinTest pinAnalog power supply +5 VAnalog power supply +5 VNot connectedNot connectedMicronas23BSP 3505DPRELIMINARY DATA SHEETPin No.PLCC68-pin27–28–293031323334353637383940414243–––4445474849505152PSDIP-pin56–55–5453525150494847454443–4241–––4039383736353433–PSDIP52-pin45–44–434241–4039–3837––––3635–––3433323130292827–PQFP80-pin626160595857565554535251504948474544434241403938373635343332PQFP44-pin44–43–424140393837–––––––3635–––34333231302928––Pin NameTypeConnection(if not used)Short DescriptionAVSSAVSSMONO_INNCVREFTOPSC1_IN_RSC1_IN_LASG1SC2_IN_RSC2_IN_LTPNCNCNCNCNCNCAGNDCAHVSSAHVSSNCNCCAPL_MAHVSUPNCSC1_OUT_LSC1_OUT_RVREF1NCNCNCOUTOUTINININININXXLVLVXLVLVAHVSSLVLVLVLVLVLVLVLVLVXXXLVLVXXLVLVLVXLVLVLVAnalog groundAnalog groundMono inputNot connectedReference voltageScart input 1 in, rightScart input 1 in, leftAnalog shield ground 1Scart input 2 in, rightScart input 2 in, leftTest PinNot connectedNot connectedNot connectedNot connectedNot connectedNot connectedAnalog reference volt-age high voltage partAnalog groundAnalog groundNot connectedNot connectedVolume capacitor MAINAnalog power supply 8.0 VNot connectedScart output 1, leftScart output 1, rightReference ground 1high voltage partNot connectedNot connectedNot connected24MicronasPRELIMINARY DATA SHEETBSP 3505DPin No.PLCC68-pin5354555657585960––6162636566––67––68PSDIP-pin3231302928272625––242322212019––18––17PSDIP52-pin–26–2524232221––20––191817––16––15PQFP80-pin31302928272625242322212019181716151413121110PQFP44-pin–––2726252423––22––21–––2019––18Pin NameTypeConnection(if not used)Short DescriptionNCNCNCDACM_LDACM_RVREF2NCNCNCNCRESETQNCNCNCTPDVSSDVSSDVSSDVSUPDVSUPDVSUPTPOUTININOUTOUTLVLVLVLVLVXLVLVLVLVXLVLVLVLVXXXXXXLVNot connectedNot connectedNot connectedLoudspeaker out, leftLoudspeaker out, rightReference ground 2high voltage partNot connectedNot connectedNot connectedNot connectedPower-on-resetNot connectedNot connectedNot connectedTest pinDigital groundDigital groundDigital groundDigital power supply+5 VDigital power supply+5 VDigital power supply+5 VTest pinMicronas25BSP 3505D5.3. Pin ConfigurationsTPNCTPTPTPTPTPI2C_DAI2C_CLTPDVSUPDVSSTPNCNCNCRESETQPRELIMINARY DATA SHEETNCSTANDBYQADR_SELD_CTR_OUT0D_CTR_OUT1NCNCNCNCTPXTAL_OUTXTAL_INTESTENNCTPTPAVSUP1011121314151617181920212223242526987654321686766656362616059585756555453NCNCVREF2DACM_RDACM_LNCNCNCNCNCNCVREF1SC1_OUT_RSC1_OUT_LNCAHVSUPCAPL_MBSP 3505D52515049484745442728293031323334353637383940414243AVSSMONO_INVREFTOPSC1_IN_RSC1_IN_LASG1SC2_IN_RSC2_IN_LTPNCNCNCNCNCNCAHVSSAGNDCFig. 5–6: 68-pin PLCC package26MicronasPRELIMINARY DATA SHEETBSP 3505DNCNCNCD_CTR_OUT1D_CTR_OUT0ADR_SELSTANDBYQNCI2C_CLI2C_DATPTPTPTPTPTPTPDVSUPDVSSTPNCNCNCRESETQNCNCVREF2DACM_RDACM_LNCNCNC123456710111213636261605958575655545352TPXTAL_OUTXTAL_INTESTENNCTPTPAVSUPAVSSMONO_INVREFTOPSC1_IN_RSC1_IN_LASG1SC2_IN_RSC2_IN_LTPNCNCNCNCNCAGNDCAHVSSCAPL_MAHVSUPNCSC1_OUT_LSC1_OUT_RVREF1NCNCTPNCD_CTR_OUT1D_CTR_OUT0ADR_SELSTANDBYQI2C_CLI2C_DATPTPTPTPTPTPTPDVSUPDVSSTPNCRESETQNCNCVREF2DACM_RDACM_LNC123456710525150494847454443XTAL_OUTXTAL_INTESTENNCTPTPAVSUPAVSSMONO_INVREFTOPSC1_IN_RSC1_IN_LSC2_IN_RSC2_IN_LNCNCAGNDCAHVSSCAPL_MAHVSUPNCSC1_OUT_LSC1_OUT_RVREF1NCNCBSP 3505D11121314151617181920212223242522414039383736353433323130292827BSP 3505D14151617181920212223242526272829303132515049484745444342414039383736353433Fig. 5–8: 52-pin PSDIP packageFig. 5–7: -pin PSDIP packageMicronas27BSP 3505DSC2_IN_LSC2_IN_RASG1SC1_IN_LSC1_IN_RVREFTOPNCMONO_INAVSSAVSSNCNCTPNCNCNCNCNCNCAGNDCAHVSSAHVSSNCNCPRELIMINARY DATA SHEET63626160595857565554535251504948474544434241AVSUPAVSUPTPTPNCTESTENXTAL_INXTAL_OUTTPNCNCNCD_CTR_OUT1D_CTR_OUT0ADR_SELSTANDBYQ65666768697071727374757677787980123456710111213141516171819202122232440393837363534CAPL_MAHVSUPNCSC1_OUT_LSC1_OUT_RVREF1NCNCNCNCNCNCDACM_LDACM_RVREF2NCBSP 3505D333231302928272625NCI2C_CLI2C_DATPTPTPTPTPTPTPDVSUPDVSUPTPDVSSDVSSDVSSDVSUPNCNCNCNCRESETQNCNCFig. 5–9: 80-pin PQFP package28MicronasPRELIMINARY DATA SHEETBSP 3505DNCVREF1SC1_OUT_RSC1_OUT_LNCAHVSUPDACM_LDACM_RVREF2NCNC3332313029282726252423CAPL_MAHVSSAGNDCSC2_IN_LSC2_IN_RASG1SC1_IN_LSC1_IN_RVREFTOPMONO_INAVSS34353637383940414243441AVSUPTPTPTESTENXTAL_INXTAL_OUTTP2345671011STANDBYQADR_SELD_CTR_OUT0D_CTR_OUT122212019RESETQNCDVSSDVSUPTPTPTPTPTPI2C_DAI2C_CLBSP 3505D18171615141312Fig. 5–10: 44-pin PQFP packageMicronas29BSP 3505D5.4. Pin Circuits (pin numbers refer to PLCC68 package)PRELIMINARY DATA SHEET40 kNGNDFig. 5–11: Input/Output Pins 8 and 9(I2C_DA, I2C_CL)≈ 3.75 VFig. 5–17: Input Pins 30, 31, 33, and 34 (SC1–2_IN_L/R)125 kFig. 5–12: Input Pins 11, 12, and 61(STANDBYQ, ADR_SEL, RESETQ)≈ 3.75 VFig. 5–18: Pin 42 (AGNDC)DVSUPPNGNDFig. 5–13: Output Pins 13, and 14(D_CTR_OUT0/1)Fig. 5–19: Capacitor Pin 44 (CAPL_M)0...2 VP40 pF80 k3–30 pF500 kN300≈ 3.75 V3–30 pFFig. 5–14: Input/Output Pins 20 and 21(XTALIN/OUT)Fig. 5–20: Output Pins 47, 48(SC1_OUT_L/R)VREFTOP≈2.6VAHVSUPFig. 5–15: Pin 29 (VREFTOP)0...1.2 mA24 k≈ 3.75 V3.3 kFig. 5–16: Input Pin 28 (MONO_IN)30Fig. 5–21: Output Pins 56, 57(DACM_L/R)MicronasPRELIMINARY DATA SHEETBSP 3505D5.5. Electrical Characteristics5.5.1. Absolute Maximum RatingsSymbolTATSVSUP1VSUP2VSUP3dVSUP23PTOTParameterAmbient Operating TemperatureStorage TemperatureFirst Supply VoltageSecond Supply VoltageThird Supply VoltageVoltage between AVSUP and DVSUPChip Power DissipationPLCC68 without Heat SpreaderPSDIP without Heat SpreaderPSDIP52 without Heat SpreaderPQFP44 without Heat SpreaderInput Voltage, all Digital InputsInput Current, all Digital PinsInput Voltage, all Analog InputsInput Current, all Analog InputsOutput Current, all SCART OutputsOutput Current, all Analog Outputsexcept SCART OutputsOutput Current, other pins connected to capacitors–SCn_IN_s,3)MONO_INSCn_IN_s,3)MONO_INSC1_OUT_sDACM_s3)CAPL_MAGNDCPin Name––AHVSUPDVSUPAVSUPAVSUP,DVSUPAHVSUP,DVSUP, AVSUPMin.0–40–0.3–0.3–0.3–0.5Max.701)1259.06.06.00.5Unit°C°CVVVV1200130012009601)–0.3–20–0.3–54), 5)4)mWVIdigIIdigVIanaIIanaIOanaIOanaICana1)2)3)4)5)VSUP2+0.3+20VSUP1+0.3+54), 5)4)VmA2)VmA2)4)4)For PQFP44 package, max. ambient operating temperature is 65 °C.positive value means current flowing into the circuit“n” means “1” or “2”, “s” means “L” or “R”The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground.Total chip power dissipation must not exceed absolute maximum rating.Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. Thisis a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi-mum ratings conditions for extended periods may affect device reliability.Micronas31BSP 3505D5.5.2. Recommended Operating Conditionsat TA = 0 to 70 °C (65 °C for PQFP44)SymbolVSUP1VSUP2VSUP3VREILtREILVDIGILVDIGIHtSTBYQ1ParameterFirst Supply VoltageSecond Supply VoltageThird Supply VoltageRESET Input High-Low and Low-High Transition VoltageRESET Low Time after DVSUPStable and Oscillator StartupDigital Input Low VoltageDigital Input High VoltageSTANDBYQ Setup Time beforeTurn-off of Second Supply VoltageSTANDBYQ,ADRSELADR_SEL,TESTENSTANDBYQ,DVSUPPin NameAHVSUPDVSUPAVSUPRESETQMin.7..754.750.455PRELIMINARY DATA SHEETTyp.8.05.05.0Max.8.45.255.250.8UnitVVVVSUP2µs0.20.81VSUP2VSUP2µsI2C-Bus RecommendationsVI2CILVI2CIHfI2CtI2C1tI2C2tI2C3tI2C4tI2C5tI2C6I2C-BUS Input Low VoltageI2C-BUS Input High VoltageI2C-BUS FrequencyI2C START Condition Setup TimeI2C STOP Condition Setup TimeI2C-Clock Low Pulse TimeI2C-Clock High Pulse TimeI2C-Data Setup Time BeforeRising Edge of ClockI2C-Data Hold Time after Falling Edge of ClockI2C_CL,I2C_DAI2C_CL,I2C_DACDAI2C_CLI2C_CL,I2C_DACDAI2C_CL12012050050055550.30.61.0VSUP2VSUP2MHznsnsnsnsnsnsCrystal RecommendationsfPfTOLDTEMRRC0Parallel Resonance Frequency at 12 pF Load CapacitanceAccuracy of AdjustmentFrequency Variation versus TemperatureSeries ResistanceShunt (Parallel) Capacitance–100–5086.218.432+100+50257.0MHzppmppmΩpF32MicronasPRELIMINARY DATA SHEETBSP 3505DSymbolParameterPin NameMin.Typ.Max.UnitLoad Capacitance RecommendationsCLExternal Load Capacitance1)XTAL_IN,XTAL_OUTPSDIPPLCC1.53.3pFpFAmplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF)VXCAExternal Clock AmplitudeXTAL_IN0.7VppAnalog Input and Output RecommendationsCAGNDCAGNDC-Filter-CapacitorCeramic Capacitor in ParallelCinSCVinSCVinMONORLSCCLSCCVMACFMADC-Decoupling Capacitor in front of SCART InputsSCART Input LevelInput Level, Mono InputSCART Load ResistanceSCART Load CapacitanceMain Volume CapacitorMain Filter CapacitorCAPL_MDACM_s2)–10%101+10%MONO_INSC1_OUT_s2)106.0SCn_IN_s2)AGNDC–20%–20%–20%3.3100330+20%2.02.0µFnFnFVRMSVRMSkΩnFµFnFRecommendations for Reference Voltage PinCVREFTOPVREFTOP-Filter-CapacitorCeramic Capacitor in Parallel1)VREFTOP–20%–20%10100µFnFExternal capacitors at each crystal pin to ground are required. The higher the capacitors, the lower the clockfrequency results. The nominal free running frequency should match 18.432 MHz as closely as possible. Dueto different layouts of customer PCBs, the matching capacitor size should be defined in the application. The sug-gested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.“n” means “1” or “2”, “s” means “L” or “R”2)Micronas33BSP 3505D5.5.3. CharacteristicsPRELIMINARY DATA SHEETat TA = 0 to 70 °C (65 °C for PQFP44), fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.4 V, VSUP2 = 4.75 to 5.25 V for min./max. valuesat TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction TemperatureMAIN (M) = Loudspeaker Channel, AUX (A) = Headphone ChannelSymbolfCLOCKDCLOCKtJITTERVxtalDCtStartupISUP1AParameterClock Input FrequencyClock High to Low RatioClock Jitter (Verification not provided in Production test)DC-Voltage OscillatorOscillator Startup Time at VDD Slew-rate of 1 V/1 µsFirst Supply Current (active)Analog Volume for Main and Aux at 0dBAnalog Volume for Main and Aux at –30dBPin NameXTAL_INMin.Typ.18.432Max.UnitMHzTest Conditions455550%ps2.5XTAL_IN,XTAL_OUTAHVSUP9.66.3DVSUPAVSUPAHVSUP86153.517.111.295255.624.616.1102357.70.42VmsmAmAmAmAmASTANDBYQ = lowISUP2AISUP3AISUP1SSecond Supply Current (active)Third Supply Current (active)First Supply Current (standby mode) at Tj = 27 °CI2C-Data Output Low VoltageI2C-Data Output High CurrentI2C-Data Output Hold Time after Falling Edge of ClockI2C-Data Output Setup Time before Rising Edge of ClockVI2COLII2COHtI2COL1tI2COL2I2C_DA0.41.0VµAnsII2COL = 3 mAVI2COH = 5 VI2C_DA,I2C_CL15100nsfI2C = 1 MHzAnalog GroundVAGNDC0RoutAGNAGNDC Open Circuit VoltageAGNDC Output ResistanceAGNDC3.63703.731253.83180VkΩRload ≥10 MΩ3 V ≤VAGNDC ≤4 VAnalog Input ResistanceRinSCRinMONOSCART Input Resistancefrom TA = 0 to 70 °CMONO Input Resistancefrom TA = 0 to 70 °CSCn_IN_s1)254058kΩfsignal = 1 kHz, I = 0.05 mAfsignal = 1 kHz, I = 0.1 mAMONO_IN152435kΩAudio Analog-to-Digital-ConverterVAICLEffective Analog Input ClippingLevel for Analog-to-Digital-ConversionSCn_IN_s,1)MONO_IN2.002.25VRMSfsignal = 1 kHz1)“n” means “1”, or “2”; “s” means “L” or “R”34MicronasPRELIMINARY DATA SHEETBSP 3505DSymbolParameterPin NameMin.Typ.Max.UnitTest ConditionsSCART OutputsRoutSCSCART Output Resistanceat Tj = 27 °Cfrom TA = 0 to 70 °CDeviation of DC-Level at SCARTOutput from AGNDC VoltageGain from Analog Inputto SCART OutputFrequency Response from AnalogInput to SCART Outputbandwidth: 0 to 20000 HzEffective Signal Level at SCART-Output during full-scale digital in-put signal from DSPSCn_IN_s1)MONO_IN →SC1_OUT_s1)SC1_OUT_s1)200200–70330460500+70ΩΩmVfsignal = 1 kHz, I = 0.1 mAdVOUTSCASCtoSCfrSCtoSC–1.0+0.5dBfsignal = 1 kHzwith resp. to 1 kHz–0.5+0.5dBVoutSCSC1_OUT_s1)1.81.92.0VRMSfsignal = 1 kHzMain OutputsRoutMAMain Output Resistanceat Tj = 27 °Cfrom TA = 0 to 70 °CDC-Level at Main-Outputfor Analog Volume at 0 dBfor Analog Volume at –30 dBEffective Signal Level at Main-Out-put during full-scale digital inputsignal from DSP for Analog Vol-ume at 0 dBDACM_s1)2.12.13.34.65.0kΩkΩfsignal = 1 kHz, I = 0.1 mAVoutDCMA1.82.04611.372.28VmVVRMSfsignal = 1 kHzVoutMA1.231.51Analog PerformanceSNRSignal-to-Noise Ratiofrom Analog Input to SCART OutputMONO_IN,SCn_IN_s1) →SC1_OUT_s1)9396dBInput Level = –20 dB, fsig = 1 kHz, equally weighted 20 Hz...20 kHzTHDTotal Harmonic Distortionfrom Analog Input to SCART OutputMONO_IN,SCn_IN_s1) →SC1_OUT_s1)0.010.03%Input Level = –3 dBr,fsig = 1 kHz, equally weighted 20 Hz...20 kHz1)“n” means “1” or “2”; “s” means “L” or “R”Micronas35BSP 3505DPRELIMINARY DATA SHEETSymbolXTALKParameterCrosstalk attenuation– PLCC68 – PSDIPPin NameMin.Typ.Max.UnitTest ConditionsInput Level = –3 dB, fsig = 1 kHz, unused ana-log inputs connected toground by Z < 1 kΩequally weighted 20 Hz...20 kHzbetween left and right channel within SCART Input/Output pair (L→R, R→L)SCn_IN1) →SC1_OUTPLCC68PSDIP8080dBdBPSRR: rejection of noise on AHVSUP at 1 kHzAGNDCFrom Analog Input to SCART OutputAGNDCMONO_IN,SCn_IN_s1)SC1_OUT_s1)VREFTOP2.48070dBdBDCVREFTOP1)DC voltage at VREFTOP2.62.7V“n” means “1” or “2”; “s” means “L” or “R”36MicronasPRELIMINARY DATA SHEETBSP 3505D6. Application CircuitC s. section 5.5.2.10 µF+3.3 µF+100 nF100 nF18.432MHz+8.0 V+10 µFXTAL_OUT (63) 20VREFTOP (54) 29CAPL_M (40) 44AGNDC (42) 42XTAL_IN (62) 211 µF1 µF28 (55) MONO_IN330 nFDACM_L (29) 561 nFDACM_R (28) 57MAIN31 (52) SC1_IN_L330 nF30 (53) SC1_IN_R330 nFAHVSS330 nF330 nF32 (51) ASG134 (49) SC2_IN_L33 (50) SC2_IN_RSC1_OUT_L (37) 47100Ω22 µF+BSP 3505DSC1_OUT_R (36) 48D_CTR_OUT0 (5) 13D_CTR_OUT1 (4) 14100Ω22 µF+5V5VDVSSDVSS8 (10) I2C_DA9 (9) I2C_CLAVSS61 (24) RESETQ45 (39) AHVSUP67 (18) DVSUP43 (41) AHVSSTESTEN (61) 2211 (7) STANDBYQ12 (6) ADR_SEL26 (57) AVSUP49 (35) VREF1100 nFResetQ(from CCU,seesection.3.3.)+10 µF100 nFAVSS100 nF5 V5 V8.0 VNote: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP package.Application Note:All ground pins should be connected to one low-resistiveground plane.All supply pins should be connected separately withshort and low-resistive lines to the power supply.Decoupling capacitors from DVSUP to DVSS, AVSUP toAVSS, and AHVSUP to AHVSS are recommended asclose as possible to these pins. Decoupling of DVSUPand DVSS is most important. We recommend usingMicronasmore than one capacitor. By choosing different values,the frequency range of active decoupling can be ex-tended. In our application boards we use: 220 pF,470 pF, 1.5 nF, and 10 µF. The capacitor with lowest val-ue should be placed nearest to the DVSUP and DVSSpins.The ASG1 pin should be connected as closely as pos-sible to the MSP to ground. If it is lead with the SC1 input-lines as shielding line, it should NOT be conneted toground at the SCART connector.3758 (27) VREF266 (19) DVSS27 (56) AVSSBSP 3505DPRELIMINARY DATA SHEET38MicronasPRELIMINARY DATA SHEETBSP 3505DMicronas39BSP 3505D7. Appendix A: BSP 3505D Version HistoryA2First hardware release BSP 3505D8. Data Sheet HistoryPRELIMINARY DATA SHEET1.Preliminary Data Sheet: “BSP 3505D BasebandSound Processor”, Oct. 21, 1998, 6251-481-1PD.First release of the preliminary data sheet.Micronas GmbHHans-Bunte-Strasse 19D-79108 Freiburg (Germany)P.O. Box 840D-79008 Freiburg (Germany)Tel. +49-761-517-0 Fax +49-761-517-2174E-mail: docservice@micronas.comInternet: www.micronas.comPrinted in GermanyOrder No. 6251-481-1PDAll information and data contained in this data sheet are without anycommitment, are not to be considered as an offer for conclusion of acontract, nor shall they be construed as to create any liability. Any newissue of this data sheet invalidates previous issues. Product availabilityand delivery are exclusively subject to our respective order confirma-tion form; the same applies to orders based on development samplesdelivered. By this publication, Micronas GmbH does not assume re-sponsibility for patent infringements or other rights of third partieswhich may result from its use.Further, Micronas GmbH reserves the right to revise this publicationand to make changes to its content, at any time, without obligation tonotify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored ona retrieval system, or transmitted without the express written consentof Micronas GmbH.40Micronas
