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专利名称：Signal delay circuit
发明人：Chu, Albert Manhee,Griffin, William Robert申请号：EP88119927.7申请日：19881130公开号：EP0322577B1公开日：19930616
摘要：A signal delay circuit is provided which includes first (16) and second (10) circuitsconnected in parallel with each other. The first circuit includes serially connected first (18)and second (20) transistors of a first conductivity type, and the second circuit includesserially connected third (12) and fourth (14) transistors of a conductivity type opposite tothe first one. A fifth transistor (24) of the first conductivity type and a sixth one (26) of theopposite conductivity type are connected in parallel from the common point (B) providedbetween the first and second transistors to the common point (C) between the third andfourth transistors. A signal to be delayed is applied to one end of the parallely arrangedfirst and second circuits, and a complementary signal to the control electrodes of thetransistors.
申请人：INTERNATIONAL BUSINESS MACHINES CORPORATION
地址：OLD ORCHARD ROAD; ARMONK, N.Y. 10504
代理机构：Mönig, Anton, Dipl.-Ing.
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