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专利名称：Phase lock loop with coarse control loop
having frequency lock detector and deviceincluding same
发明人：Hyung-Rok Lee,Moon-Sang Hwang,Sang-Hyun Lee,Bong-Joon Lee,Deog-Kyoon Jeong
申请号：US11056995申请日：20050211公开号：US07102446B1公开日：20060905
专利附图：
摘要：A phase lock loop (PLL) for controlling a sampling clock or other clock, and a
data sampling circuit, transceiver, or other device including such a PLL. The PLL includes amulti-range VCO, at least one fine control loop for controlling the VCO, and a coarsecontrol loop for controlling the VCO by changing its frequency-voltage characteristic.The coarse control loop includes a frequency lock detector and voltage rangemonitoring logic. Typically, the frequency lock detector locks operation of the coarsecontrol loop when the difference between the VCO output clock frequency and areference frequency decreases to within a predetermined threshold, and the unlockedcoarse control loop employs the voltage range monitoring logic to change the VCOfrequency-voltage characteristic when the VCO's fine control voltage leaves apredetermined range. Other aspects are a transceiver (including at least two receiverinterfaces and a transmitter interface) implementing a clocking scheme employing nomore than three PLLs for clock generation, and a transceiver having a multi-layeredreceiver interface including digital circuitry and a single clock-generating PLL (an analogPLL for generating a multiphase clock to be shared by all layers of the receiver interface).Each receiver interface layer performs blind oversampling on a different received signalusing the multiphase clock and the digital circuitry includes multilayered digital phaselock loop circuitry which receives the oversampled data.
申请人：Hyung-Rok Lee,Moon-Sang Hwang,Sang-Hyun Lee,Bong-Joon Lee,Deog-Kyoon Jeong
地址：Sunnyvale CA US,Yong-In-Si KR,Cupertino CA US,Seoul KR,Seoul KR
国籍：US,KR,US,KR,KR
代理机构：Girard & Equitz LLP
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