TMS320F28335的时钟介绍

作者：Free 文章来源：Free 点击数：85 更新时间：2010-8-26

TMS320F28335上有一个基于PLL电路的片上时钟模块，为CPU及外设提供时钟有两种方式：一种是用外部的时钟源，将其连接到X1引脚上或者

XCLKIN引脚上，X2接地；另一种是使用振荡器产生时钟，用30MHz的晶体和两个20PF的电容组成的电路分别连接到X1和X2引脚上，XCLKIN引脚

接地。我们常用第二种来产生时钟。此时钟将通过一个内部PLL锁相环电路，进行倍频。由于F28335的最大工作频率是150M，所以倍频值最大

是5。其中倍频值由PLLCR的低四位和PLLSTS的第7、8位来决定。其详细的倍频值可以参照TMS320F28335的Datasheet。下面是F28335的时钟设 置：

void InitPll(Uint16 val, Uint16 divsel) {

// Make sure the PLL is not running in limp mode if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) {

// Missing external clock has been detected // Replace this line with a call to an appropriate // SystemShutdown(); function. asm(\" ESTOP0\"); }

// DIVSEL MUST be 0 before PLLCR can be changed from // 0x0000. It is set to 0 by an external reset XRSn // This puts us in 1/4

if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) {

EALLOW;

SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; EDIS; }

// Change the PLLCR

if (SysCtrlRegs.PLLCR.bit.DIV != val) {

EALLOW;

// Before setting PLLCR turn off missing clock detect logic SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; SysCtrlRegs.PLLCR.bit.DIV = val; EDIS;

// Optional: Wait for PLL to lock.

// During this time the CPU will switch to OSCCLK/2 until // the PLL is stable. Once the PLL is stable the CPU will // switch to the new PLL value. //

// This time-to-lock is monitored by a PLL lock counter. //

// Code is not required to sit and wait for the PLL to lock. // However, if the code does anything that is timing critical, // and requires the correct clock be locked, then it is best to // wait until this switching has completed.

// Wait for the PLL lock bit to be set.

// The watchdog should be disabled before this loop, or fed within // the loop via ServiceDog().

// Uncomment to disable the watchdog DisableDog();

while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) {

// Uncomment to service the watchdog // ServiceDog(); }

EALLOW;

SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; EDIS; }

// If switching to 1/2 if((divsel == 1)||(divsel == 2)) {

EALLOW;

SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; EDIS; }

// If switching to 1/1

// * First go to 1/2 and let the power settle

// The time required will depend on the system, this is only an example // * Then switch to 1/1 if(divsel == 3) {

EALLOW;

SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; DELAY_US(50L);

SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; EDIS; } }

如果我们希望DSP工作在某一个频率下，我们就可以对Uint16 val, Uint16 divsel两个参数进行设定。