Table4–104.Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path
Maximum DCD (ps) for Row DDIO Output I/O
Standard
3.3-V LVTTL3.3-V LVCMOS2.5V1.8V
1.5-V LVCMOSSSTL-2 Class ISSTL-2 Class IISSTL-18 Class I1.8-V HSTL Class I1.5-V HSTL Class ILVDS
StratixIIGX Devices (PLL Output Feeding
DDIO)
-3 Device
1106575851056560505055180
Unit
pspspspspspspspspspsps
-4 and -5 Device
10575901001007570657070180
Table4–105.Maximum DCD for DDIO Output on Column I/O Pins With PLL in the Clock Path(Part 1 of2)
Maximum DCD (ps) for Stratix II GX Devices (PLL Output Feeding
DDIO)Column DDIO Output I/O
Standard-3 Device-4 and -5 Device
3.3-V LVTTL3.3-V LVCMOS2.5V1.8V
1.5-V LVCMOSSSTL-2 Class ISSTL-2 Class IISSTL-18 Class ISSTL-18 Class II1.8-V HSTL Class I1.8-V HSTL Class II1.5-V HSTL Class I1.5-V HSTL Class II
14510085851406560507060605585
1601109510015575706580707070100
Unit
pspspspspspspspspspspspsps
Table4–105.Maximum DCD for DDIO Output on Column I/O Pins With PLL in the Clock Path(Part 2 of2)
Maximum DCD (ps) for Stratix II GX Devices (PLL Output Feeding
DDIO)Column DDIO Output I/O
Standard-3 Device-4 and -5 Device
1.2-V HSTLLVPECL
155180
155180
Unit
psps
High-Speed I/O
Specifications
Table4–106 provides high-speed timing specifications definitions.
Table4–106.High-Speed Timing Specifications and DefinitionsHigh-Speed Timing Specifications
tCfHSCLKJWtRISEtFALL
Timing unit interval (TUI)
Definitions
High-speed receiver/transmitter input and output clock period.High-speed receiver/transmitter input and output clock frequency.Deserialization factor (width of parallel data bus).PLL multiplication factor.Low-to-high transmission time.High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = tC/w).Fast PLL input clock frequency
Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA.Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA.The timing difference between the fastest and the slowest output edges including tCO variation and clock skew across channels driven by the same fast PLL. The clock is included in the TCCS measurement.The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.Peak-to-peak output jitter on high-speed PLLs.Duty cycle on high-speed transmitter output clock.Lock time for high-speed transmitter and receiver PLLs.
fINfHSDRfHSDRDPA
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitterOutput jittertDUTYtLOCK
Table4–107 shows the high-speed I/O timing specifications for -3 speed grade StratixIIGX devices.
Table4–107.High-Speed I/O Specifications for -3 Speed Grade
Symbol
fIN = fHSDR / W
Notes(1), (2)
-3 Speed GradeMin
1616150150(4)(4)150-330
Conditions
W = 2 to 32 (LVDS, HyperTransport technology) (3)
W = 1 (SERDES bypass, LVDS only)W = 1 (SERDES used, LVDS only)
TypMax
5205007171,0407605001,040200-190160180
Unit
MHzMHzMHzMbpsMbpsMbpsMbpspspspspsps%UIUINumber of repetitions
fHSDR (data rate)
J = 4 to 10 (LVDS, HyperTransport technology)J = 2 (LVDS, HyperTransport technology)J = 1 (LVDS only)
fHSDRDPA (DPA data rate)J = 4 to 10 (LVDS, HyperTransport technology)TCCSSWOutput jitterOutput tRISEOutput tFALLtDUTY
DPA run lengthDPA jitter tolerance (5)DPA lock time
SPI-4
Parallel Rapid I/OMiscellaneous
0000000000111111111100001111100100001010101001010101
(1)(2)(3)(4)
All differential standardsAll differential standardsAll differential I/O standardsAll differential I/O standards
455055 6,400
Data channel peak-to-peak jitter0.44
10%25%50%100%
256256256256256
(5)
When J = 4 to 10, the SERDES block is used.When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clockfrequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.
For setup details, refer to the characterization report.
