SN65lvds93

LVDSSERDESTRANSMITTER

FEATURES

28:4DataChannelCompressionatupto1.904GigabitsperSecondThroughputSuitedforPoint-to-PointSubsystemCommunicationWithVeryLowEMI

28DataChannelsPlusClockinLow-VoltageTTLand4DataChannelsPlusClockOutLow-VoltageDifferential

SelectableRisingorFallingClockEdgeTriggeredInputs

BusPinsTolerate6-kVHBMESD

OperatesFromaSingle3.3-VSupplyand250mW(Typ)

5-VTolerantDataInputs

PackagedinThinShrinkSmall-OutlinePackageWith20MilTerminalPitchConsumes<1mWWhenDisabled

WidePhase-LockInputFrequencyRange20MHzto68MHz

NoExternalComponentsRequiredforPLLOutputsMeetorExceedtheRequirementsofANSIEIA/TIA-4Standard

IndustrialTemperatureQualifiedTA=–40°Cto85°C

ReplacementfortheDS90CR285

•••

•••••••••••

Whentransmitting,databitsD0throughD27areeachloadedintoregistersupontheedgeoftheinputclocksignal(CLKIN).Therisingorfallingedgeoftheclockcanbeselectedviatheclockselect(CLKSEL)pin.ThefrequencyofCLKINismultipliedseventimesandthenusedtoseriallyunloadthedataregistersin7-bitslices.Thefourserialstreamsandaphase-lockedclock(CLKOUT)arethenoutputtoLVDSoutputdrivers.ThefrequencyofCLKOUTisthesameastheinputclock,CLKIN.

DGG PACKAGE(TOP VIEW)

DESCRIPTION

TheSN65LVDS93LVDSserdes(serializer/deserializer)transmittercontainsfour7-bitparallel-loadserial-outshiftregisters,a7נclocksynthesizer,andfivelow-voltagedifferentialsignaling(LVDS)driversinasingleintegratedcircuit.Thesefunctionsallow28bitsofsingle-endedLVTTLdatatobesynchronouslytransmittedoverfivebalanced-pairconductorsforreceiptbyacompatiblereceiver,suchastheSN65LVDS94.

VCCD5D6D7GNDD8D9D10VCCD11D12D13GNDD14D15D16CLKSEL

D17D18D19GNDD20D21D22D23VCCD24D25

1234 56710111213141516171819202122232425262728565554535251504948474544434241403938373635343332313029D4D3D2GNDD1D0D27

LVDSGNDY1MY1PY2MY2P

LVDSVCCLVDSGNDY3MY3P

CLKOUTMCLKOUTPY4MY4P

LVDSGNDPLLGNDPLLVCCPLLGNDSHTDNCLKIND26GND

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.

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Thesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.

DESCRIPTION(CONTINUED)

TheSN65LVDS93requiresnoexternalcomponentsandlittleornocontrol.Thedatabusappearsthesameattheinputtothetransmitterandoutputofthereceiverwiththedatatransmissiontransparenttotheuser(s).TheonlyuserinterventionisselectingaclockrisingedgebyinputtingahighleveltoCLKSELorafallingedgewithalow-levelinputandthepossibleuseoftheshutdown/clear(SHTDN).SHTDNisanactive-lowinputtoinhibittheclockandshutofftheLVDSoutputdriversforlowerpowerconsumption.Alowlevelonthissignalclearsallinternalregistersatalowlevel.

TheSN65LVDS93ischaracterizedforoperationoverambientairtemperaturesof–40°Cto85°C.

FUNCTIONALBLOCKDIAGARAM

Parallel-Load󰀀7-BitShift󰀀RegisterA,B,󰀀...GSHIFT/LOADCLKParallel-Load󰀀7-BitShift󰀀RegisterA,B,󰀀...GSHIFT/LOADCLKParallel-Load󰀀7-BitShift󰀀RegisterA,B,󰀀...GSHIFT/LOADD0,󰀀D1,󰀀D2,󰀀D3,

D4,󰀀D6,󰀀D7

7Y0PY0M

D8,󰀀D9,󰀀D12,󰀀D13,D14,󰀀D15,󰀀D18

7Y1PY1M

D19,󰀀D20,󰀀D21,󰀀D22,D24,󰀀D25,󰀀D26

7Y2PY2M

Input󰀀BusCLKParallel-Load󰀀7-BitShift󰀀RegisterA,B,󰀀...GSHIFT/LOADCLKD27,󰀀D5,󰀀D10,󰀀D11,D16,󰀀D17,󰀀D23

7Y3PY3M

Control󰀀LogicSHTDN7×Clock/PLL7×CLKCLKINCLKSEL

CLKCLKINHRISING/FALLINGEDGECLKOUTPCLKOUTM

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D0

CLKIN

orCLKIN

CLKOUT

NextCyclePrevious CycleY0

D0–1D7D6Current CycleD4D3D2D1D0D7+1Y1

D8–1D18D15D14D13D12D9D8D18+1Y2

D19–1D26D25D24D22D21D20D19D26+1Y3D27–1D23D17D16D11D10D5D27D23+1Figure1.Typical'LVDS93LoadandShiftSequences

EQUIVALENTINPUTANDOUTPUTSCHEMATICDIAGRAMS

VCCVCC5 ΩDn orSHTDN10 kΩ50 Ω7 V7 V300 kΩYnP or YnM

INPUTOUTPUT

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ABSOLUTEMAXIMUMRATINGS

overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)

UNIT

VCCVOVI

Supplyvoltagerange(2)

VoltagerangeatanyoutputterminalVoltagerangeatanyinputterminal

BusPins(Class3A)

Electrostaticdischarge(3)

BusPins(Class2B)BusPins(Class2A)BusPins(Class2B)

Continuoustotalpowerdissipation

TATstg

Operatingfree-airtemperaturerangeStoragetemperaturerange

Leadtemperature1,6mm(1/16inch)fromcasefor10seconds

(1)(2)(3)

–0.5Vto4V-0.5VtoVCC+0.5V–0.5Vto5.5V

6KV400V6KV200V

SeeDissipationRatingTable

–40°Cto85°C–65°Cto150°C

260°C

Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.AllvoltagevaluesarewithrespecttotheGNDterminals.

ThisratingismeasuredusingMIL-STD-883CMethod,3015.7.

DISSIPATIONRATINGTABLE

PACKAGEDGG(1)

TA≤25°CPOWERRATING

1377mW

DERATINGFACTOR(1)

ABOVETA=25°C

11mW/°C

TA=70°CPOWERRATING

882mW

TA=85°CPOWERRATING

717mW

Thisistheinverseofthejunction-to-ambientthermalresistancewhenboard-mountedandwithnoairflow.

RECOMMENDEDOPERATINGCONDITIONS

MIN

VCCVIHVILZLTA

SupplyvoltageHigh-levelinputvoltageLow-levelinputvoltageDifferentialloadimpedanceOperatingfree-airtemperature

90–4032

0.813285

NOM3.3

MAX3.6

UNITVVVΩ°C

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ELECTRICALCHARACTERISTICS

overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted)

PARAMETERVT|VOD|Δ|VOD|VOC(SS)VOC(PP)IIHIILIOSIOZInputvoltagethresholdDifferentialsteady-stateoutputvoltagemagnitudeChangeinthesteady-statedifferentialoutputvoltagemagnitudebetweenoppositebinarystatesSteady-statecommon-modeoutputvoltagePeak-to-peakcommon-modeoutputvoltageHigh-levelinputcurrentLow-levelinputcurrentShort-circuitoutputcurrentHigh-impedancestateoutputcurrentVIH=VCCVIL=0VVOY=0VVOD=0VVO=0VtoVCCDisabled,AllinputsatGNDICC(AVG)Quiescentcurrent(average)Ci(1)

InputcapacitanceAlltypicalvaluesareatVCC=3.3V,TA=25°C.

Enabled,RL=100Ω(5places),Worst-casepattern(seeFigure4),tc=15.38ns953RL=100Ω,SeeFigure3SeeFigure31.125247TESTCONDITIONSMINTYP(1)1.4454501.37515020±10±24±12±20350120MAXUNITVmVmVVmVµAµAmAmAµAµAmApFTIMINGREQUIREMENTS

MINNOMMAXtctwtttsuthInputclockperiodHigh-levelinputclockpulsewidthdurationInputsignaltransitiontimeDatasetuptime,D0throughD27beforeCLKIN↑orCLKIN↓(seeFigure2)Dataholdtime,D0throughD27afterCLKIN↓orCLKIN↑(seeFigure2)31.514.70.4tctc500.6tc5UNITnsnsnsnsnsCopyright©1998–2009,TexasInstrumentsIncorporatedSubmitDocumentationFeedback

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SWITCHINGCHARACTERISTICS

overrecommendedoperatingconditions(unlessotherwisenoted)

PARAMETERt0t1Delaytime,CLKOUT↑toserialbitposition0Delaytime,CLKOUT↑toserialbitposition1TESTCONDITIONSMIN–0.201t*0.207c2t*0.207c3t*0.207c4t*0.207c5t*0.207c6t*0.207cTYP(1)0MAX0.201t)0.207c2t)0.207c3t)0.207c4t)0.207c5t)0.207c6t)0.207cUNITnsnst2Delaytime,CLKOUT↑serialbitposition2nst3Delaytime,CLKOUT↑serialbitposition3tc=15.38ns(±0.2%),|Inputclockjitter|<50ps(2),SeeFigure5nst4Delaytime,CLKOUT↑toserialbitposition4nst5Delaytime,CLKOUT↑toserialbitposition5nst6tsk(o)Delaytime,CLKOUT↑toserialbitposition6nsOutput skew,tn*ntc7–0.20tc=15.38ns(±0.2%),|Inputclockjitter|<50ps(2),SeeFigure5tc=15.38ns+0.75sin(2π500E3t)±0.05ns,SeeFigure6tc=15.38ns+0.75sin(2π3E6t)±0.05ns,SeeFigure60.20nst7tc(o)Delaytime,CLKIN↓orCLKIN↑toCLKOUT↑Outputclockperiod(3)4.2tc±80±3004t7cnspspsnsps1500psmsnsΔtc(o)Outputclockcycle-to-cyclejittertwtttentdis(1)(2)(3)

High-leveloutputclockpulsedurationDifferentialoutputvoltagetransitiontime(trortf)SeeFigure3Enabletime,SHTDN↑tophaselock(Ynvalid)Disabletime,SHTDN↓tooff-state(CLKOUTlow)SeeFigure7SeeFigure82607001250AlltypicalvaluesareatVCC=3.3V,TA=25°C.

Inputclockjitteristhemagnitudeofthechargeintheinputclockperiod

Theoutputclockjitteristhechangeintheoutputclockperiodfromonecycletothenextcycleobservedover15,000cycles.

PARAMETERMEASUREMENTINFORMATION

tsuDn

thCLKINnote:

Allinputtimingisdefinedat1.4Vonaninputsignalwitha10%to90%riseorfalltimeoflessthan5ns.

CLKSEL LOWCLKSEL HIGH

Figure2.SetupandHoldTimeDefinition

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PARAMETERMEASUREMENTINFORMATION(continued)

YP49.9 Ω ± 1% (2 Places)

VODYMCL = 10 pF Max(2 Places)NOTE A:The lumped instrumentation capacitance for any

single-ended voltage measurement is less than or equalto 10 pF. When making measurements at YP or YM, thecomplementary output is similarly loaded.

(a) SCHEMATIC

100%VOD(H)0 VVOD(L)20%0%tftr80%VOCVOC(PP)VOC(SS)VOC(SS)0 V(b) WAVEFORMSFigure3.TestLoadandVoltageDefinitionsforLVDSOutputs

tcCLKINEven DnOdd Dn

NOTE A:The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with

CLKSEL low shown.

Figure4.Worst-CaseTestPattern(CLKSELLowShown)

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PARAMETERMEASUREMENTINFORMATION(continued)

t7CLKIN

CLKOUT

t6t5t4t3t2t1t0Yn

≈ 2.5 V

CLKIN

1.4 V≈ 0.5 V

td7

td0 – td6

CLKOUT

orYn

VOD(H)0.00 VVOD(L)

Figure5.TimingDefinitions

Reference

+

∑

+

Modulation

VCO

DeviceUnderTest

V(t) = A sin (2 π f(mod) t)

HP8656BSignal Generator0.1 MHz – 990 MHz

HP8665A

Synthesized Signal

Generator

0.1 MHz – 4200 MHz

OUTPUT

Modulation Input

Device Under Test

DTS2070CDigital Time Scope

CLKINCLKOUTInput

RF Output

Figure6.OutputClockJitterTestSetup

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PARAMETERMEASUREMENTINFORMATION(continued)

CLKIN

Dn

tenSHTDNYnInvalidValidFigure7.EnableTimeWaveforms(CLKSELlowshown)

CLKIN

tdisSHTDNCLKOUT

Figure8.DisableTimeWaveforms(CLKSELlowshown)

TYPICALCHARACTERISTICS

WORST-CASESUPPLYCURRENT

vs

FREQUENCY120VCC = 3.6 V100ICC− Supply Current − mA80VCC = 3 VVCC = 3.3 V604020030

40

5060

f − Frequency − MHz

70

Figure9.

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APPLICATIONINFORMATION

16-BITBUSEXTENSION

Ina16-bitbusapplication(Figure10),TTLdataandclockcomingfrombustransceiversthatinterfacethebackplanebusarriveattheTxparallelinputsoftheLVDSserdestransmitter.Theclockassociatedwiththebusisalsoconnectedtothedevice.Theon-chipPLLsynchronizesthisclockwiththeparalleldataattheinput.ThedataisthenmultiplexedintothreedifferentlinedriverswhichperformtheTTLtoLVDSconversion.TheclockisalsoconvertedtoLVDSandpresentedtoaseparatedriver.ThissynchronizedLVDSdataandclockatthereceiver,whichrecoverstheLVDSdataandclock,performsaconversionbacktoTTL.Dataisthendemultiplexedintoaparallelformat.Anon-chipPLLsynchronizesthereceivedclockwiththeparalleldata,andthenallarepresentedtotheparalleloutputportofthereceiver.

16-BitBTL BusInterface

TTLInterfaceD0–D78LVDSInterface0 To 10 Meters(Media Dependent)

SN65LVDS93SN65LVDS94TTL

Interface816-BitBTL BusInterface

SN74FB2032D0–D7SN74FB2032SN74FB2032D8–D1588D8–D15SN74FB2032CLKBackplaneBus

XMIT ClockRCV ClockCLKBackplaneBus

Figure10.16-BitBusExtension

16-BITBUSEXTENSIONWITHPARITY

Inthepreviousapplicationwedidnothaveacheckingbitthatwouldprovideassurancethatthedatacrossesthelink.Ifweaddaparitybittothepreviousexample,wewouldhaveadiagramsimilartotheoneinFigure11.ThedevicefollowingtheSN74FB2032isalow-costparitygenerator.Eachtransmit-sidetransceiver/paritygeneratortakestheLVTTLdatafromthecorrespondingtransceiver,performsaparitycalculationoverthebyte,andthenpassesthebitswithitscalculatedparityvalueontheparallelinputoftheLVDSserdestransmitter.Again,theon-chipPLLsynchronizesthistransmitclockwiththeeighteenparallelbits(16data+2parity)attheinput.ThesynchronizedLVDSdata/parityandclockarriveatthereceiver.

ThereceiverperformstheconversionfromLVDStoLVTTLandthetransceiver/paritygeneratorperformstheparitycalculations.Thesedevicescomparetheircorrespondinginputbyteswiththevaluereceivedontheparitybit.Thetransceiver/paritygeneratorwillassertitsparityerroroutputifamismatchisdetected.

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LVDSInterface0 To 10 Meters(Media Dependent)

SN65LVDS93SN74FB2032D0–D7 Bit LatchableTransceiver/ WithParity GeneratorParitySN65LVDS948Parity9 Bit LatchableTransceiver/ WithParity GeneratorD0–D7SN74FB203216-BitBTL BusInterface

TTLInterface

TTLInterfaceW/ParityTTLInterfaceW/Parity

TTLInterface

16-BitBTL BusInterface

D8–D15SN74FB20329 Bit LatchableTransceiver/ WithParity Generator8Parity8Parity9 Bit LatchableTransceiver/ WithParity GeneratorD8–D15SN74FB2032ParityErrorCLKBackplaneBus

XMIT ClockRCV ClockCLKBackplaneBus

Figure11.16-BitBusExtensionWithParity

lowcostvirtualbackplanetransceiver

Figure12representsLVDSserdesinanapplicationasavirtualbackplanetransceiver(VBT).TheconceptofaVBTcanbeachievedbyimplementingindividualLVDSserdeschipsetsinbothdirectionsofsubsystemserializedlinks.

Dependingontheapplication,thedesignerwillfacevaryingchoiceswhenimplementingaVBT.InadditiontothedevicesshowninFigure12,functionssuchasparityanddelaylinesforcontrolsignalscouldbeincluded.Usingadditionalcircuitry,half-duplexorfull-duplexoperationcanbeachievedbyconfiguringtheclockandcontrollinesproperly.

ThedesignermaychoosetoimplementanindependentclockoscillatorateachendofthelinkandthenuseaPLLtosynchronizeLVDSserdes'sparallelI/Otothebackplanebus.ResynchronizingFIFOsmayalsoberequired.

BusTransceiversBackplane

Bus

BusTransceiversTTLInputsUp To21 or 28BitsLVDS SerdesTransmitterLVDSSerial Links4 or 5PairsLVDS SerdesTransmitterLVDS SerdesReceiverLVDS SerdesReceiverTTLOutputsUp To21 or 28BitsBusTransceiversBackplaneBus

BusTransceiversFigure12.VirtualBackplaneTransceiver

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PACKAGEOPTIONADDENDUM

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PACKAGINGINFORMATION

OrderableDeviceSN65LVDS93DGGSN65LVDS93DGGG4SN65LVDS93DGGRSN65LVDS93DGGRG4

(1)

Status(1)ACTIVEACTIVEACTIVEACTIVE

PackageTypeTSSOPTSSOPTSSOPTSSOP

PackageDrawingDGGDGGDGGDGG

PinsPackageEcoPlan(2)

Qty56565656

3535

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

MSLPeakTemp(3)Level-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEAR

2000Green(RoHS&

noSb/Br)2000Green(RoHS&

noSb/Br)

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.

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Addendum-Page1

PACKAGEMATERIALSINFORMATION

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TAPEANDREELINFORMATION

*Alldimensionsarenominal

Device

PackagePackagePinsTypeDrawingTSSOP

DGG

56

SPQ

ReelReelA0DiameterWidth(mm)(mm)W1(mm)330.0

24.4

8.6

B0(mm)15.6

K0(mm)1.8

P1(mm)12.0

WPin1(mm)Quadrant24.0

Q1

SN65LVDS93DGGR2000

PackMaterials-Page1

PACKAGEMATERIALSINFORMATION

www.ti.com

14-Jul-2012

*Alldimensionsarenominal

Device

SN65LVDS93DGGR

PackageType

TSSOP

PackageDrawing

DGG

Pins56

SPQ2000

Length(mm)

367.0

Width(mm)367.0

Height(mm)

45.0

PackMaterials-Page2

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 MECHANICAL DATA DGG (R-PDSO-G**) 48 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,50480,270,17250,08M6,206,008,307,900,15 NOMGage Plane0,250°–8°A0,750,50124Seating Plane1,20 MAX0,150,05PINS **DIMA MAX0,10485612,6014,1017,10A MIN12,4013,9016,904040078/F 12/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IMPORTANTNOTICE

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TIhasspecificallydesignatedcertaincomponentswhichmeetISO/TS16949requirements,mainlyforautomotiveuse.Componentswhichhavenotbeensodesignatedareneitherdesignednorintendedforautomotiveuse;andTIwillnotberesponsibleforanyfailureofsuchcomponentstomeetsuchrequirements.ProductsAudioAmplifiersDataConvertersDLP®ProductsDSP

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