专利内容由知识产权出版社提供
专利名称：Race logic circuit发明人：Hoi Jun Yoo,Se Joong Lee申请号：US100462申请日：20020329公开号：US06661256B2公开日：20031209
专利附图：
摘要：A race logic circuit of the present invention includes: a WTA circuit for receivingan operand logic signal and outputting only a high signal which is the first to arriveamong the operand logic signals; plural race lines for inputting the operand logic signalinto the WTA circuit; a clock distribution line having plural delay devices connected in
series, both ends of the respective delay devices being connected to a triggering line, theclock distribution line receiving an external clock and outputting a triggering signal intothe triggering line; and plural operand logic signal input switches which are triggered bythe triggering signal output from the triggering line, for deciding whether to input theoperand logic signal into the race line. According to the race logic of the presentinvention makes it possible to compose various logic circuits. Especially, when realizingthe race logic circuit as integrated circuits, time delay due to the transistors can beremoved during the logic operation. Further, time delay in the interconnection lines isactively utilized to enhance the system speed.
申请人：KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
代理机构：Marger Johnson & McCollom, P.C.
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