CS51414EDR8G资料

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CS51411, CS51412,CS51413, CS51414

1.5 A, 260 kHz and 520 kHz,Low Voltage Buck

Regulators with ExternalBias or SynchronizationCapability

The CS5141X products are 1.5 A buck regulator ICs. These devicesare fixed−frequency operating at 260 kHz and 520 kHz. The regulatorsuse the V2™control architecture to provide unmatched transientresponse, the best overall regulation and the simplest loopcompensation for today’s high−speed logic. These productsaccommodate input voltages from 4.5 V to 40 V.

The CS51411 and CS51413 contain synchronization circuitry. TheCS51412 and CS51414 have the option of powering the controllerfrom an external 3.3 V to 6.0 V supply in order to improve efficiency,especially in high input voltage, light load conditions.

The on−chip NPN transistor is capable of providing a minimum of1.5 A of output current, and is biased by an external “boost” capacitorto ensure saturation, thus minimizing on−chip power dissipation.Protection circuitry includes thermal shutdown, cycle−by−cyclecurrent limiting and frequency foldback. The CS51411 and CS51413are functionally pin−compatible with the LT1375. The CS51412 andCS51414 are functionally pin−compatible with the LT1376.

Features

81SOIC−8D SUFFIXCASE 7511http://onsemi.com

MARKING DIAGRAMS85141xALYWyG181CS5141xyAWLYYWWGG18118−LEAD DFNMN SUFFIXCASE 505•V2 Architecture Provides Ultrafast Transient Response, Improved••••••••••

Regulation and Simplified Design

2.0% Error Amp Reference Voltage Tolerance

Switch Frequency Decrease of 4:1 in Short Circuit ConditionsReduces Short Circuit Power Dissipation

BOOST Lead Allows “Bootstrapped” Operation to MaximizeEfficiency

Sync Function for Parallel Supply Operation or Noise MinimizationShutdown Lead Provides Power−Down Option85 mA Quiescent Current During Power−DownThermal ShutdownSoft−Start

Pin−Compatible with LT1375 and LT1376Pb−Free Packages are Available

5141x=Device Codex = 1, 2, 3 or 4A=Assembly LocationL, WL=Wafer LotY, YY=YearW, WW=Work Weeky = E or GG=Pb−Free PackageORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 18 of this data sheet.

February, 2007 − Rev. 17

Publication Order Number:

CS51411/D

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CS51411, CS51412, CS51413, CS51414

PIN CONNECTIONS

CS51411/3

BOOST

VINVSWSHDNB

8VCVFBGNDSYNC

BOOST

VINVINVINVswVSWVSWSHDNB

1234567

CS51411/3

181716151413121110NCVCVFBNCNCGNDNCNCSYNC

BOOST

VINVINVINVswVSWVSWBIASNC

1234567

CS51412/4

181716151413121110NCVCVFBNCNCGNDNCNC

SHDNB

CS51412/4

BOOST

VINVSWBIAS

8VCVFBGNDSHDNB

PACKAGE PIN DESCRIPTION

SOIC−8Package Pin #

DFN18Package Pin #

Pin SymbolBOOST

Function

The BOOST pin provides additional drive voltage to the on−chip NPNpower transistor. The resulting decrease in switch on voltage increasesefficiency.

This pin is the main power input to the IC.

This is the connection to the emitter of the on−chip NPN power transistorand serves as the switch output to the inductor. This pin may be

subjected to negative voltages during switch off−time. A catch diode isrequired to clamp the pin voltage in normal operation. This node canstand −1.0 V for less than 50 ns during switch node flyback.

The BIAS pin connects to the on−chip power rail and allows the IC to runmost of its internal circuitry from the regulated output or another lowvoltage supply to improve efficiency. The BIAS pin is left floating if thisfeature is not used.

This pin provides the synchronization input.

(CS51412/CS51414)

(CS51411/CS51413)

1316

SYNCSHDNB

The shutdown pin is active low and TTL compatible. The IC goes intosleep mode, drawing less than 85 mA when the pin voltage is pulledbelow 1.0 V. This pin should be left floating in normal position.Power return connection for the IC.

The FB pin provides input to the inverting input of the error amplifier. IfVFB is lower than 0.29 V, the oscillator frequency is divided by four, andcurrent limit folds back to about 1 A. These features protect the IC undersevere overcurrent or short circuit conditions.

The VC pin provides a connection point to the output of the error

amplifier and input to the PWM comparator. Driving of this pin should beavoided because on−chip test circuitry becomes active whenevercurrent exceeding 0.5 mA is forced into the IC.No Connection

2, 3, 45, 6, 7

VINVSW

(CS51412/CS51414)

8BIAS

(CS51411/CS51413)5

(CS51412/CS51414)

(CS51411/CS51413)

GNDVFB

817

−9, 11, 12, 14, 15, 18NC

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CS51411, CS51412, CS51413, CS51414

PRODUCT SELECTION GUIDE

Part NumberCS51411ECS51411GCS51412ECS51412GCS51413ECS51413GCS51414ECS51414G

Frequency260 kHz260 kHz260 kHz260 kHz520 kHz520 kHz520 kHz520 kHz

Temperature Range−40°C to 85°C0°C to 70°C−40°C to 85°C0°C to 70°C−40°C to 85°C0°C to 70°C−40°C to 85°C0°C to 70°C

Bias/SyncSyncSyncBiasBiasSyncSyncBiasBias

D14.5 V − 16 V

C2100 mFShutdownSYNC45U12VINSHDNBSYNCVC8C40.1 mF1BOOSTCS51411/3GND6VFB7VSW3C10.1 mF1N4148L115 mHD31N58213.3 V

R1205C3100 mFR2127Figure 1. Application Diagram, 4.5 V − 16 V to 3.3 V @ 1.0 A Converter

MAXIMUM RATINGS

Rating

Operating Junction Temperature Range, TJLead Temperature Soldering: Storage Temperature Range, TS

ESD Damage Threshold (Human Body Model)

Reflow: (SMD styles only) (Note 1)

Value−40 to 150230 peak−65 to +150

2.0

Unit°C°C°CkV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.

1.60 second maximum above 183°C.

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CS51411, CS51412, CS51413, CS51414

MAXIMUM RATINGS

Pin Name

VINBOOSTVSWVCSHDNBSYNCBIASVFBGND

VMax40 V40 V40 V7.0 V7.0 V7.0 V7.0 V7.0 V7.0 V

VMIN−0.3 V−0.3 V

−0.6 V/−1.0 V, t < 50 ns

−0.3 V−0.3 V−0.3 V−0.3 V−0.3 V−0.3 V

ISOURCEN/AN/A4.0 A1.0 mA1.0 mA1.0 mA1.0 mA1.0 mA50 mA

ISINK4.0 A100 mA10 mA1.0 mA1.0 mA1.0 mA50 mA1.0 mA1.0 mA

ELECTRICAL CHARACTERISTICS (−40°C < TJ < 125°C (CS51411E/2E/3E/4E); −40°C < TA < 85°C (CS51411E/2E/3E/4E);

0°C < TA < 70°C (CS51411G/2G/3G/4G), 4.5 V< VIN < 40 V; unless otherwise specified.)

Characteristic

Oscillator

Operating FrequencyOperating FrequencyFrequency Line RegulationMaximum Duty Cycle

VFB Frequency Foldback ThresholdPWM Comparator

Slope Compensation VoltageMinimum Output Pulse WidthPower SwitchCurrent LimitFoldback CurrentSaturation VoltageCurrent Limit DelayError Amplifier

Internal Reference VoltageReference PSRRFB Input Bias CurrentOutput Source CurrentOutput Sink CurrentOutput High VoltageOutput Low VoltageUnity Gain BandwidthOpen Loop Amplifier GainAmplifier Transconductance

(Note 2)

−

VC = 1.270 V, VFB = 1.0 VVC = 1.270 V, VFB = 2.0 VVFB = 1.0 VVFB = 2.0 V(Note 2)(Note 2)(Note 2)

−

1.244−−15151.395.0−−−

1.270400.0225251.4620500706.4

1.296−0.135351.5360−−−

VdBmAmAmAVmVkHzdBmA/V

VFB > 0.36 VVFB < 0.29 V

IOUT = 1.5 A, VBOOST = VIN + 2.5 V(Note 2)

1.60.90.4−

2.31.50.7120

3.02.11.0160

AAVns

CS51411/CS51412, Fix VFB, DVC/DTONCS51413/CS51414

CS51411/CS51412, VFB to VSWCS51413/CS51414, VFB to VSW

8.025−−

1750150−

2675300230

mV/msmV/msnsns

CS51411/CS51412CS51413/CS51414

−−−

224446−850.29

2605200.05900.32

2965940.15950.36

kHzkHz%/V%V

Test Conditions

Min

Typ

Max

Unit

2.Guaranteed by design, not 100% tested in production.

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 125°C (CS51411E/2E/3E/4E); −40°C < TA < 85°C (CS51411E/2E/3E/4E);

0°C < TA < 70°C (CS51411G/2G/3G/4G), 4.5 V< VIN < 40 V; unless otherwise specified.)

Characteristic

Sync

Sync Frequency RangeSync Frequency RangeSync Pin Bias CurrentSync Threshold VoltageShutdown

Shutdown Threshold VoltageShutdown Pin Bias CurrentThermal ShutdownOvertemperature Trip PointThermal Shutdown HysteresisGeneral

Quiescent Current

Shutdown Quiescent CurrentBoost Operating CurrentMinimum Boost VoltageStartup Voltage

Minimum Output Current

3.Guaranteed by design, not 100% tested in production.

ISW = 0 AVSHDNB = 0 VVBOOST − VSW = 2.5 V(Note 3)

−−

3.08.06.0−2.2−

4.02015−3.37.0

6.2585402.54.412

mAmAmA/AVVmA

(Note 3)(Note 3)

175−

18542

195−

°C°C

VSHDNB = 0 V

−

1.00.14

1.35.00

1.635

VmA

CS51411/CS51412CS51413/CS51414VSYNC = 0 VVSYNC = 5.0 V

−

305575−2501.0

−−0.13601.5

4708800.24601.9

kHzkHzmAmAV

Test Conditions

Min

Typ

Max

Unit

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CS51411, CS51412, CS51413, CS51414

SHDNBVIN5.0 mA2.9 V LDOVoltageRegulatorShutdownComparator+−+1.3 V−SRQSYNCBIASArtificialRampOscillatorThermalShutdownBOOST

OutputDriverVSW

∑+−PWMComparator−VFB+−−+1.270 VErrorAmplifier+0.32 V−+Frequencyand CurrentLimit FoldbackIFOLDBACKCurrentLimitComparatorIREF+−GNDVC

1.46 VFigure 2. Block Diagram

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CS51411, CS51412, CS51413, CS51414

APPLICATIONS INFORMATION

THEORY OF OPERATION

V2 Control

The CS5141X family of buck regulators utilizes a V2control technique and provides a high level of integration toenable high power density design optimization.

Every pulse width modulated controller configures basiccontrol elements such that when connected to the feedbacksignal of a power converter, sufficient loop gain andbandwidth is available to regulate the voltage set pointagainst line and load variations. The arrangement of theseelements differentiates a voltage mode, or a current modecontroller from a V2 device.

Figure 3 illustrates the basic architecture of a V2controller.

Error Amplifier

−+Z2VREFVFBClockV2 Control RampZ1VO

cycle modulation to occur. Actual oscilloscope waveformstaken from the converter show the switch node VSWITCH,the error signal VC and the feedback signal VFB (ACcomponent only) are shown in Figure 5.

S1L1VO

D1C1R1VINDuty CycleBuckControllerSlopeCompOscillatorLatchSRSFB+−PWMComparatorV2 ControlFigure 3. V2 Control

Figure 4. Buck Converter with V2 Control

In common with V mode or I mode, the feedback signalis compared with a reference voltage to develop an errorsignal which is fed to one input of the PWM. The secondinput to the PWM, however, is neither a fixed voltage rampnor the switch current, but rather the feedback signal fromthe output of the converter. This feedback signal providesboth DC information as well as AC information (the controlramp) for the converter to regulate its set point. The controlarchitecture is known as V2 since both PWM inputs arederived from the converter’s output voltage. This is a littlemisleading because the control ramp is typically generatedfrom current information present in the converter.

The feedback signal from the buck converter shown inFigure 4 is processed in one of two ways before being routedto the inputs of the PWM comparator. The Fast Feedbackpath (FFB) adds slope compensation to the feedback signalbefore passing it to one input of the PWM. The SlowFeedback path (SFB) compares the original feedback signalagainst a DC reference. The error signal generated at theoutput of the error amplifier VC is filtered by a lowfrequency pole before being routed to the second input of thePWM. Each switch cycle is initiated (S1 on), when theoutput latch is set by the oscillator. Each switch cycleterminates (S1 off), when the FFB signal (AC plus outputDC) exceeds SFB (error DC), and the output latch is reset.In the event of a load transient, the FFB signal changesfaster, in relation to the filtered SFB signal, causing duty

In the event of a load transient, the FFB signal changesfaster, in relation to the filtered SFB signal, causing dutycycle modulation to occur. By this means the converter’stransient response time is independent of the error amplifierbandwidth. The error amplifier is used here to ensureexcellent DC accuracy.

In order for the controller to operate optimally, a stableramp is required at the feedback pin.

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−+SwitchLatch/DrivePWMFigure 5.

+FFBR2VCVREF+−ErrorAmplifierVSWITCH

VCVFB

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CS51411, CS51412, CS51413, CS51414

Control Ramp Generation

In original V2 designs, the control ramp VCR wasgenerated from the converter’s output ripple. Using a currentderived ramp provides the same benefits as current mode,namely input feed forward, single pole output filtercompensation and fast feedback following output loadtransients. Typically a tantalum or organic polymercapacitor is selected having a sufficiently large ESRcomponent, relative to its capacitive and ESL ripplecontributions, to ensure the control ramp was sensinginductor current and its amplitude was sufficient to maintainloop stability. This technique is illustrated in Figure 6.

VIN

LCesrCVOUTVIN

RCVOUT

VFBFigure 7. Control Ramp Generated from DCR

Inductor Sensing

VFBFigure 6. Control Ramp Generated from Output

Advances in multilayer ceramic capacitor technology aresuch that MLCC’s can provide a cost effective filter solutionfor low voltage (< 12 V), high frequency converters(>200 kHz). For example, a 10 mF MLCC 16 V in a805 SMT package has an ESR of 2 mW and an ESL of100 nH. Using several MLCC’s in parallel, connected topower and ground planes on a PCB with multiple vias, canprovide a “near perfect” capacitor. Using this technique,output switching ripple below 10 mV can be readilyobtained since parasitic ESR and ESL ripple contributionsare nil. In this case, the control ramp is generated elsewherein the circuit.

Ramp generation using dcr inductor current sensing,where the L/DCR time constant of the output inductor ismatched with the CR time constant of the integratingnetwork, is shown in Figure 7. The converter’s transientresponse following a 1 A step load is shown in Figure 8. Thistransient response is indicative of a closed loop in excess of10 kHz having good gain and phase margin in the frequencydomain. Also note the amplitude of output switching rippleprovided by just two 10 mF MLCC’s.

Figure 8.

Ramp generation using a voltage feed forward techniqueis illustrated in Figure 9.

VIN

RfCZVOUT

CfVFBFigure 9. Control Ramp from Voltage Feed Forward

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CS51411, CS51412, CS51413, CS51414

Some representative efficiency data is shown in Figure 10.

10080EFFICIENCY (%)6040Vin = 5.5 V, Vout= 3.3 V20Vin = 7.5 V, Vout = 5.0 VVin = 15V, Vout = 12 V0

05001000IOUT, OUTPUT CURRENT (mA)

1500Figure 11. A CS51411 Buck Regulator is Synced by an

External 350 kHz Pulse SignalPower Switch and Current Limit

Figure 10. Efficiency versus Output Current

More detailed information is available in the ONSemiconductor application note AND8276/D on V2 and theCS5141x demonstration board number.

Error Amplifier

VIN − VSW (V)The CS5141X has a transconductance error amplifier,whose noninverting input is connected to an InternalReference Voltage generated from the on−chip regulator. Theinverting input connects to the VFB pin. The output of theerror amplifier is made available at the VC pin. A typicalfrequency compensation requires only a 0.1 mF capacitorconnected between the VC pin and ground, as shown inFigure 1. This capacitor and error amplifier’s outputresistance (approximately 8.0 MW) create a low frequencypole to limit the bandwidth. Since V2 control does not requirea high bandwidth error amplifier, the frequencycompensation is greatly simplified.

The VC pin is clamped below Output High Voltage. Thisallows the regulator to recover quickly from overcurrent orshort circuit conditions.

Oscillator and Sync Feature (CS51411 and CS51413 only)

The collector of the built−in NPN power switch isconnected to the VIN pin, and the emitter to the VSW pin.When the switch turns on, the VSW voltage is equal to theVIN minus switch Saturation Voltage. In the buck regulator,the VSW voltage swings to one diode drop below groundwhen the power switch turns off, and the inductor current iscommutated to the catch diode. Due to the presence of highpulsed current, the traces connecting the VSW pin, inductorand diode should be kept as short as possible to minimize thenoise and radiation. For the same reason, the input capacitorshould be placed close to the VIN pin and the anode of thediode.

The saturation voltage of the power switch is dependenton the switching current, as shown in Figure 12.

0.70.60.50.40.30.20.100

0.51.0SWITCHING CURRENT (A)

1.5

The on−chip oscillator is trimmed at the factory and requiresno external components for frequency control. The highswitching frequency allows smaller external components to beused, resulting in a board area and cost savings. The tightfrequency tolerance simplifies magnetic components election.The switching frequency is reduced to 25% of the nominalvalue when the VFB pin voltage is below Frequency FoldbackThreshold. In short circuit or overload conditions, this reducesthe power dissipation of the IC and external components.An external clock signal can sync CS51411/CS51414 to ahigher frequency. The rising edge of the sync pulse turns on thepower switch to start a new switching cycle, as shown inFigure 11. There is approximately 0.5 ms delay between therising edge of the sync pulse and rising edge of the VSW pinvoltage. The sync threshold is TTL logic compatible, and dutycycle of the sync pulses can vary from 10% to 90%. Thefrequency foldback feature is disabled during the sync mode.

Figure 12. The Saturation Voltage of the Power Switch

Increases with the Conducting Current

Members of the CS5141X family contain pulse−by−pulsecurrent limiting to protect the power switch and externalcomponents. When the peak of the switching current reachesthe Current Limit, the power switch turns off after theCurrent Limit Delay. The switch will not turn on until thenext switching cycle. The current limit threshold is

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CS51411, CS51412, CS51413, CS51414

independent of switching duty cycle. The maximum loadcurrent, given by the following formula under continuousconduction mode, is less than the Current Limit due to theripple current.

V(V*VO)

IO(MAX)+ILIM*OIN2(L)(VIN)(fs)

As shown in Figure 14, the BOOST pin current includes aconstant 7.0 mA predriver current and base currentproportional to switch conducting current. A detaileddiscussion of this current is conducted in ThermalConsideration section. A 0.1 mF capacitor is usually adequatefor maintaining the Boost pin voltage during the on time.

BIAS Pin (CS51412 and CS51414 Only)

BOOST PIN CURRENT (mA)where:

fS = switching frequency,ILIM = current limit threshold,VO = output voltage,VIN = input voltage,L = inductor value.

When the regulator runs undercurrent limit, thesubharmonic oscillation may cause low frequencyoscillation, as shown in Figure 13. Similar to current modecontrol, this oscillation occurs at the duty cycle greater than50% and can be alleviated by using a larger inductor value.The current limit threshold is reduced to Foldback Currentwhen the FB pin falls below Foldback Threshold. Thisfeature protects the IC and external components under thepower up or overload conditions.

The BIAS pin allows a secondary power supply to bias thecontrol circuitry of the IC. The BIAS pin voltage should bebetween 3.3 V and 6.0 V. If the BIAS pin voltage falls belowthat range, use a diode to prevent current drain from theBIAS pin. Powering the IC with a voltage lower than theregulator’s input voltage reduces the IC power dissipationand improves energy transfer efficiency.

30252015105000.51.0SWITCHING CURRENT (A)

1.5Figure 14. The Boost Pin Current Includes 7.0 mAPredriver Current and Base Current when the Switchis Turned On. The Beta Decline of the Power Switch

Further Increases the Base Current at High

Switching CurrentShutdown

Figure 13. The Regulator in Current Limit

BOOST Pin

The BOOST pin provides base driving current for thepower switch. A voltage higher than VIN provides requiredheadroom to turn on the power switch. This in turn reducesIC power dissipation and improves overall systemefficiency. The BOOST pin can be connected to an externalboost−strapping circuit which typically uses a 0.1 mF capacitorand a 1N914 or 1N4148 diode, as shown in Figure 1. When thepower switch is turned on, the voltage on the BOOST pin isequal to

VBOOST+VIN)VO*VF

The internal power switch will not turn on until the VIN pinrises above the Startup Voltage. This ensures no switchinguntil adequate supply voltage is provided to the IC.

The IC enters a sleep mode when the SHDNB pin is pulledbelow Shutdown Threshold Voltage. In the sleep mode, thepower switch keeps open and the supply current reduces toShutdown Quiescent Current. This pin has internal pull−upcurrent. So when this pin is not used, leave the SHDNB pinopen.

Startup

where:

VF = diode forward voltage.

The anode of the diode can be connected to any DC voltageother than the regulated output voltage. However, themaximum voltage on the BOOST pin shall not exceed 40 V.

During power up, the regulator tends to quickly charge upthe output capacitors to reach voltage regulation. This givesrise to an excessive in−rush current which can be detrimentalto the inductor, IC and catch diode. In V2 control, thecompensation capacitor provides Soft−Start with no needfor extra pin or circuitry. During the power up, the OutputSource Current of the error amplifier charges thecompensation capacitor which forces VC pin and thus outputvoltage ramp up gradually.

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The Soft−Start duration can be calculated by

V CCOMP

TSS+C

ISOURCE

diode current. The short circuit waveforms are captured inFigure 16, and the benefit of the foldback frequency andcurrent limit is self−evident.

where:

VC = VC pin steady−state voltage, which is approximately

equal to error amplifier’s reference voltage.

CCOMP = Compensation capacitor connected to the VC pinISOURCE = Output Source Current of the error amplifier.Using a 0.1 mF CCOMP, the calculation shows a TSS over5.0 ms which is adequate to avoid any current stresses.Figure 15 shows the gradual rise of the VC, VO and envelopeof the VSW during power up. There is no voltage overshootafter the output voltage reaches the regulation. If the supplyvoltage rises slower than the VC pin, output voltage mayovershoot.

Figure 16. In Short Circuit, the Foldback Current andFoldback Frequency Limit the Switching Current to

Protect the IC, Inductor and Catch DiodeThermal Considerations

Figure 15. The Power Up Transition of CS5141X

RegulatorShort Circuit

A calculation of the power dissipation of the IC is alwaysnecessary prior to the adoption of the regulator. The currentdrawn by the IC includes quiescent current, predrivercurrent, and power switch base current. The quiescentcurrent drives the low power circuits in the IC, whichinclude comparators, error amplifier and other logic blocks.Therefore, this current is independent of the switchingcurrent and generates power equal to

WQ+VIN IQ

When the VFB pin voltage drops below FoldbackThreshold, the regulator reduces the peak current limit by40% and switching frequency to 1/4 of the nominalfrequency. These features are designed to protect the IC andexternal components during overload or short circuitconditions. In those conditions, peak switching current isclamped to the current limit threshold. The reducedswitching frequency significantly increases the ripplecurrent, and thus lowers the DC current. The short circuit cancause the minimum duty cycle to be limited by MinimumOutput Pulse Width. The foldback frequency reduces theminimum duty cycle by extending the switching cycle. Thisprotects the IC from overheating, and also limits the powerthat can be transferred to the output. The current limitfoldback effectively reduces the current stress on theinductor and diode. When the output is shorted, the DCcurrent of the inductor and diode can approach the currentlimit threshold. Therefore, reducing the current limit by 40%can result in an equal percentage drop of the inductor and

where:

IQ = quiescent current.

The predriver current is used to turn on/off the powerswitch and is approximately equal to 12 mA in worst case.During steady state operation, the IC draws this current fromthe Boost pin when the power switch is on and then receivesit from the VIN pin when the switch is off. The predrivercurrent always returns to the VSW pin. Since the predrivercurrent goes out to the regulator’s output even when thepower switch is turned off, a minimum load is required toprevent overvoltage in light load conditions. If the Boost pinvoltage is equal to VIN + VO when the switch is on, the powerdissipation due to predriver current can be calculated by

WDRV+12mA (VIN*VO)O)VIN

The base current of a bipolar transistor is equal to collectorcurrent divided by beta of the device. Beta of 60 is used hereto estimate the base current. The Boost pin provides the basecurrent when the transistor needs to be on.

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The power dissipated by the IC due to this current is

V2I

WBASE+O S

60VIN

where:

IS = DC switching current.

When the power switch turns on, the saturation voltageand conduction current contribute to the power loss of anon−ideal switch. The power loss can be quantified as

WSAT+

IS VSATVIN

where:

VSAT = saturation voltage of the power switch which is

shown in Figure 12.The switching loss occurs when the switch experiencesboth high current and voltage during each switch transition.This regulator has a 30 ns turn−off time and associatedpower loss is equal to

I VIN

WS+S 30ns fS

Internal bias to the IC can be supplied via the Vin pin or theBIAS pin. When the BIAS pin is low, the logic turns P2 onand current is routed to the internal bias circuitry from theVin pin. Conversely, when the BIAS pin is high, the logicturns P1 on and current is routed to the internal bias circuitryfrom the BIAS pin.

Here is an example of the power savings:

The input voltage range for Vin is 4.5 V to 40 V. The inputvoltage range for BIAS is 3.3 V to 6 V. The quiescent currentspecification is 3 mA (min), 4 mA (typ), and 6.25 mA (max).Using a typical battery voltage of 14 V and the typicalquiescent current number of 4 mA, the power would be:

P+V I+14 4e−3+56mW

We’ll assume the BIAS pin is connected to an externalregulator at 5 V instead of the output voltage. The BIAS pinwould normally be connected to the output voltage, butadding an added switching regulator efficiency number herewould cloud this example. Now the internal BIAS circuitryis being powered via 5 V. The resulting on chip power beingdissipated is:

P+V I+5 4e−3+21mW

The turn−on time is much shorter and thus turn−on loss isnot considered here.

The total power dissipated by the IC is sum of all the above

WIC+WQ)WDRV)WBASE)WSAT)WS

The IC junction temperature can be calculated from theambient temperature, IC power dissipation and thermalresistance of the package. The equation is shown as follows,

TJ+WIC RqJA)TA

The power savings is 35 mW.

Now, to demonstrate more notable savings using themaximum battery input voltage of 40 V, the maximumquiescent current of 6.25 mA, and the lowest allowed BIASvoltage for proper operation of 3.3 V;Powered from Vin:

P+40 6.25e−3+250mW

The maximum IC junction temperature shall not exceed125°C to guarantee proper operation and avoid any damagesto the IC.

Using the BIAS Pin

Powered from the BIAS pin:

P+3.3 6.25e−3+21mW

The power savings is 229 mW.

Minimum Load Requirement

The efficiency savings in using the BIAS pin is mostnotable at low load and high input voltage as will beexplained below.

Figure 17 will help to understand the increase in efficiencywhen the BIAS pin is used. The circuitry shown is not theactual implementation, but is useful in the explanation.

P1InternalBIASAs pointed out in the previous section, a minimum load isrequired for this regulator due to the predriver currentfeeding the output. Placing a resistor equal to VO divided by12 mA should prevent any voltage overshoot at light loadconditions. Alternatively, the feedback resistors can bevalued properly to consume 12 mA current.

COMPONENT SELECTION

Input Capacitor

BIAS

Vin

P2In a buck converter, the input capacitor witnesses pulsedcurrent with an amplitude equal to the load current. Thispulsed current and the ESR of the input capacitors determinethe VIN ripple voltage, which is shown in Figure 18. For VINripple, low ESR is a critical requirement for the inputcapacitor selection. The pulsed input current possesses asignificant AC component, which is absorbed by the inputcapacitors.

Figure 17.

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The RMS current of the input capacitor can be calculatedusing:

IRMS+IOǸD(1*D)

where:

D = switching duty cycle which is equal to VO/VIN.IO = load current.

Selecting the capacitor type is determined by eachdesign’s constraint and emphasis. The aluminumelectrolytic capacitors are widely available at lowest cost.Their ESR and Equivalent Series Inductor (ESL) arerelatively high. Multiple capacitors are usually paralleled toachieve lower ESR. In addition, electrolytic capacitorsusually need to be paralleled with a ceramic capacitor forfiltering high frequency noises. The OS−CON are solidaluminum electrolytic capacitors, and therefore has a muchlower ESR. Recently, the price of the OS−CON capacitorshas dropped significantly so that it is now feasible to usethem for some low cost designs. Electrolytic capacitors arephysically large, and not used in applications where the size,and especially height is the major concern.

Ceramic capacitors are now available in values over 10 mF.Since the ceramic capacitor has low ESR and ESL, a singleceramic capacitor can be adequate for both low frequencyand high frequency noises. The disadvantage of ceramiccapacitors are their high cost. Solid tantalum capacitors canhave low ESR and small size. However, the reliability of thetantalum capacitor is always a concern in the applicationwhere the capacitor may experience surge current.

Output Capacitor

Figure 18. Input Voltage Ripple in a Buck Converter

To calculate the RMS current, multiply the load currentwith the constant given by Figure 19 at each duty cycle. It isa common practice to select the input capacitor with an RMScurrent rating more than half the maximum load current. Ifmultiple capacitors are paralleled, the RMS current for eachcapacitor should be the total current divided by the numberof capacitors.

0.60.50.4IRMS (XIO)0.30.20.1000.20.60.4DUTY CYCLE

0.81.0In a buck converter, the requirements on the outputcapacitor are not as critical as those on the input capacitor.The current to the output capacitor comes from the inductorand thus is triangular. In most applications, this makes theRMS ripple current not an issue in selecting outputcapacitors.

The output ripple voltage is the sum of a triangular wavecaused by ripple current flowing through ESR, and a squarewave due to ESL. Capacitive reactance is assumed to besmall compared to ESR and ESL. The peak−to−peak ripplecurrent of the inductor is:

V(V*VO)

IP*P+OIN

(VIN)(L)(fS)

VRIPPLE(ESR), the output ripple due to the ESR, is equalto the product of IP−P and ESR. The voltage developedacross the ESL is proportional to the di/dt of the outputcapacitor. It is realized that the di/dt of the output capacitoris the same as the di/dt of the inductor current. Therefore,when the switch turns on, the di/dt is equal to (VIN − VO)/L,and it becomes VO/L when the switch turns off. The totalripple voltage induced by ESL can then be derived from

V*VOVV

VRIPPLE(ESL)+ESL(IN))ESL(IN)+ESL(IN)LLL

Figure 19. Input Capacitor RMS Current can be

Calculated by Multiplying Y Value with Maximum Load

Current at any Duty Cycle

The total output ripple is the sum of the VRIPPLE(ESR) andVRIPPLE(ESR).

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Figure 20. The Output Voltage Ripple Using Two 10 mF

Ceramic Capacitors in Parallel

Figure 22. The Output Voltage Ripple Using

One 100 mF OS−CON

Figure 21. The Output Voltage Ripple Using One 100 mF

POSCAP Capacitor

Figure 23. The Output Voltage Ripple Using

One 100 mF Tantalum Capacitor

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Figure 20 to Figure 23 show the output ripple of a 5.0 Vto 3.3 V/500 mA regulator using 22 mH inductor and variouscapacitor types. At the switching frequency, the low ESRand ESL make the ceramic capacitors behave capacitivelyas shown in Figure 20. Additional paralleled ceramiccapacitors will further reduce the ripple voltage, butinevitably increase the cost. “POSCAP”, manufactured bySANYO, is a solid electrolytic capacitor. The anode issintered tantalum and the cathode is a highly conductivepolymerized organic semiconductor. TPC series, featuringlow ESR and low profile, is used in the measurement ofFigure 21. It is shown that POSCAP presents a good balanceof capacitance and ESR, compared with a ceramic capacitor.In this application, the low ESR generates less than 5.0 mVof ripple and the ESL is almost unnoticeable. The ESL of thethrough−hole OS−CON capacitor give rise to the inductiveimpedance. It is evident from Figure 22 which shows thestep rise of the output ripple on the switch turn−on and largespike on the switch turn−off. The ESL prevents the outputcapacitor from quickly charging up the parasitic capacitor ofthe inductor when the switch node is pulled below groundthrough the catch diode conduction. This results in the spikeassociated with the falling edge of the switch node. The Dpackage tantalum capacitor used in Figure 23 has the samefootprint as the POSCAP, but doubles the height. The ESRof the tantalum capacitor is apparently higher than thePOSCAP. The electrolytic and tantalum capacitors providea low−cost solution with compromised performance. Thereliability of the tantalum capacitor is not a serious concernfor output filtering because the output capacitor is usuallyfree of surge current and voltage.

Diode Selection

The worse case of the diode average current occurs duringmaximum load current and maximum input voltage. For thediode to survive the short circuit condition, the current ratingof the diode should be equal to the Foldback Current Limit.See Table 1 for Schottky diodes from ON Semiconductorwhich are suggested for CS5141X regulator.

Inductor Selection

When choosing inductors, one might have to considermaximum load current, core and copper losses, componentheight, output ripple, EMI, saturation and cost. Lowerinductor values are chosen to reduce the physical size of theinductor. Higher value cuts down the ripple current, corelosses and allows more output current. For mostapplications, the inductor value falls in the range between2.2 mH and 22 mH. The saturation current ratings of theinductor shall not exceed the IL(PK), calculated according to

V(V*VO)

IL(PK)+IO)OIN

2(fS)(L)(VIN)

The diode in the buck converter provides the inductorcurrent path when the power switch turns off. The peakreverse voltage is equal to the maximum input voltage. Thepeak conducting current is clamped by the current limit ofthe IC. The average current can be calculated from:

I(V*VO)

ID(AVG)+OIN

VIN

The DC current through the inductor is equal to the loadcurrent. The worse case occurs during maximum loadcurrent. Check the vendor’s spec to adjust the inductor valueundercurrent loading. Inductors can lose over 50% ofinductance when it nears saturation.

The core materials have a significant effect on inductorperformance. The ferrite core has benefits of small physicalsize, and very low power dissipation. But be careful not tooperate these inductors too far beyond their maximumratings for peak current, as this will saturate the core.Powered Iron cores are low cost and have a more gradualsaturation curve. The cores with an open magnetic path, suchas rod or barrel, tend to generate high magnetic fieldradiation. However, they are usually cheap and small. Thecores providing a close magnetic loop, such as pot−core andtoroid, generate low electro−magnetic interference (EMI).There are many magnetic component vendors providingstandard product lines suitable for CS5141X. Table 2 liststhree vendors, their products and contact information.

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Table 1.

Part Number1N58171N58181N5819MBR0520MBR0530MBR0540MBRS120MBRS130MBRS140

VBREAKDOWN (V)

203040203040203040

IAVERAGE (A)

1.01.01.00.50.50.51.01.01.0

V(F) (V) @ IAVERAGE

0.450.550.60.3850.430.530.550.3950.6

PackageAxial LeadAxial LeadAxial LeadSOD−123SOD−123SOD−123SMBSMBSMB

Table 2.

VendorCoiltronics

Product Family

UNI−Pac1/2: SMT, barrel

THIN−PAC: SMT, toroid, low profile

CTX: Leaded, toroidDO1608: SMT, barrel

DS/DT 1608: SMT, barrel, magnetically shielded

DO3316: SMT, barrel

DS/DT 3316: SMT, barrel, magnetically shielded

DO3308: SMT, barrel, low profile

−

Web Sitewww.coiltronics.com

Telephone(516) 241−7876

Coilcraftwww.coilcraft.com(800) 322−25

Pulsewww.pulseeng.com(619) 674−8100

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5.0 V − 12 V inputC122 mFU1245VIN7VFBBOOST1VSW38C20.1 mFC50.1 mFR2373D21N4148SHDNBCS51411/3SYNCGND6VC15 mHL1D1MBR0520C622 mR3127

C30.01 mFR150 kC40.1 mF−5.0 V outputFigure 24. Additional Application Diagram, 5.0 V − 12 V to −5.0 V/400 mA Inverting Converter

D21N4148D112 V

C1100 mFShutdownU12VIN5SHDNB4BIAS1BOOST3C10.1 mFVSW1N4148CS51412/4GND6VFB7L115 mHD31N58215.0 V

R1373C3100 mFVC8C40.1 mFR2127Figure 25. Additional Application Diagram, 12 V to 5.0 V/1.0 A Buck Converter using the BIAS Pin

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ORDERING INFORMATION

Device

CS51411ED8CS51411ED8GCS51411EDR8CS51411EDR8GCS51411EMNR2GCS51412ED8CS51412ED8GCS51412EDR8CS51412EDR8GCS51412EMNR2GCS51413ED8CS51413ED8GCS51413EDR8CS51413EDR8GCS51413EMNR2GCS51414ED8CS51414ED8GCS51414EDR8CS51414EDR8GCS51414EMNR2GCS51411GD8CS51411GD8GCS51411GDR8CS51411GDR8GCS51411GMNR2GCS51412GD8CS51412GD8GCS51412GDR8CS51412GDR8GCS51412GMNR2GCS51413GD8CS51413GD8GCS51413GDR8CS51413GDR8GCS51413GMNR2GCS51414GD8CS51414GD8GCS51414GDR8CS51414GDR8GCS51414GMNR2G

0°C < TA < 70°C−40°C < TA < 85°COperating Temperature Range

PackageSOIC−8SOIC−8 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)DFN18 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)DFN18 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)DFN18 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)DFN18 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)DFN18 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)DFN18 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)DFN18 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)

SOIC−8SOIC−8 (Pb−Free)DFN18 (Pb−Free)

Shipping†98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel2500 Tape & Reel98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel2500 Tape & Reel98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel2500 Tape & Reel98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel2500 Tape & Reel98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel2500 Tape & Reel98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel2500 Tape & Reel98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel2500 Tape & Reel98 Units/Rail98 Units/Rail2500 Tape & Reel2500 Tape & Reel2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

SOIC−8 NBCASE 751−07ISSUE AH

−X−A85NOTES:

1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDEMOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6.751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

MILLIMETERSMINMAX4.805.003.804.001.351.750.330.511.27 BSC0.100.250.190.250.401.270 _8 _0.250.505.806.20INCHES

MINMAX0.10.1970.1500.1570.0530.0690.0130.0200.050 BSC0.0040.0100.0070.0100.0160.0500 _8 _0.0100.0200.2280.244B1S40.25 (0.010)MYM−Y−GKC−Z−HD0.25 (0.010)

MSEATINGPLANENX 45_0.10 (0.004)MJZY

SDIMABCDGHJKMNSSOLDERING FOOTPRINT*

1.520.0607.00.2754.00.1550.60.0241.2700.050SCALE 6:1

mmǓǒinches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

PACKAGE THERMAL DATA

Parameter

RqJCRqJATypicalTypical

SOIC−845165

Unit°C/W°C/W

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PACKAGE DIMENSIONS

DFN18CASE 505−01ISSUE C

DABNOTES:

1.DIMENSIONS AND TOLERANCING PERASME Y14.5M, 1994.

2.DIMENSIONS IN MILLIMETERS.3.DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN0.25 AND 0.30 MM FROM TERMINAL

4.COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.

DIMAA1A3bDD2EE2eKL

MILLIMETERSMINMAX0.801.000.000.050.20 REF0.180.306.00 BSC3.984.285.00 BSC2.983.280.50 BSC0.20−−−0.450.65

PIN 1 LOCATION2XE0.15C2X0.15C0.10C18XTOP VIEW(A3)A0.08CSIDE VIEWD218XA1CSEATINGPLANESOLDERING FOOTPRINT*

5.3018XLe1910.7518XK1810E24.1918X0.30PITCHBOTTOM VIEW

b0.10CAB0.05C

NOTE 3

0.30

18X

3.24DIMENSIONS: MILLIMETERS*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

PACKAGE THERMAL DATA

Parameter

RqJA

Typical

DFN1835

Unit°C/W

V2 is a trademark of Switch Power, Inc.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: orderlit@onsemi.comN. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81−3−5773−3850ON Semiconductor Website: www.onsemi.comOrder Literature: http://www.onsemi.com/orderlitFor additional information, please contact your localSales Representativehttp://onsemi.com20CS51411/D

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