Am29LV320D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both AdvancedMicro Devices and Fujitsu. Although the document is marked with the name of the company that orig-inally developed the specification, these products will be offered to customers of both AMD andFujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Anychanges that have been made are the result of normal datasheet improvement and are noted in thedocument revision summary, where supported. Future routine revisions will occur when appropriate,and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To orderthese products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansionmemory solutions.
Publication Number 23579 Revision CAmendment +6 Issue DateNovember 15, 2004
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Am29LV320D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■Secured Silicon (SecSiTM Sector)
— Kbyte Sector Size; Replacement/substitute
devices (such as Mirrorbit™) have 256 bytes.—Factory locked and identifiable: 16 bytes (8
words) available for secure, random factory Electronic Serial Number; verifiable as factory
locked through autoselect function.
ExpressFlash option allows entire sector to be available for factory-secured data
—Customer lockable: Can be programmed once
and then permanently locked after being shipped from AMD■Zero Power Operation
—Sophisticated power management circuits
reduce power consumed during inactive periods to nearly zero.
■Package options
—48-pinTSOP—48-ball FBGA■Sector Architecture
—Eight 8 Kbyte sectors
—Sixty-three Kbyte sectors■Top or bottom boot block
■Manufactured on 0.23 µm process
technology
■Compatible with JEDEC standards
—Pinout and software compatible with
single-power-supply flash standard
■Minimum 1 million erase cycles guaranteed
per sector
■20 Year data retention at 125°C
—Reliable operation for the life of the system
SOFTWARE FEATURES
■Supports Common Flash Memory Interface
(CFI)
■Erase Suspend/Erase Resume
—Suspends erase operations to allow
programming in non-suspended sectors
■Data# Polling and Toggle Bits
—Provides a software method of detecting the
status of program or erase cycles
■Unlock Bypass Program command
—Reduces overall programming time when
issuing multiple program command sequences
HARDWARE FEATURES
■Any combination of sectors can be erased ■Ready/Busy# output (RY/BY#)
—Hardware method for detecting program or
erase cycle completion
■Hardware reset pin (RESET#)
—Hardware method of resetting the internal
state machine to the read mode
■WP#/ACC input pin
—Write protect (WP#) function allows protection
of two outermost boot sectors, regardless of sector protect status
—Acceleration (ACC) function provides
accelerated program times
■Sector protection
—Hardware method of locking a sector, either
in-system or using programming equipment, to prevent any program or erase operation within that sector
—Temporary Sector Unprotect allows changing
data in protected sectors in-system
PERFORMANCE CHARACTERISTICS
■High performance
—Access time as fast 90 ns
—Program time: 7µs/word typical utilizing
Accelerate function
■Ultra low power consumption (typical
values)
—2 mA active read current at 1 MHz—10 mA active read current at 5 MHz
—200 nA in standby or automatic sleep mode
Publication# 23579Rev: CAmendment/+6Issue Date: November 15, 2004
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GENERAL DESCRIPTION
The Am29LV320D is a 32 megabit, 3.0volt-only flash memory device, organized as2,097,152 words of 16 bits each or 4,194,304bytes of 8 bits each. Word mode data appearson DQ0–DQ15; byte mode data appears onDQ0–DQ7. The device is designed to be pro-grammed in-system with the standard 3.0 voltVCC supply, andcan also be programmed instandard EPROM programmers.
The device is available with an access time of90 or 120 ns. The devices are offered in 48-pinTSOP and 48-ball FBGA packages. Standardcontrol pins—chip enable (CE#), write enable(WE#), and output enable (OE#)—control nor-mal read and write operations, and avoid buscontention issues.
The device requires only a single 3.0 voltpower supply for both read and write func-tions. Internally generated and regulated volt-ages are provided for the program and eraseoperations.
tomer code (programmed through AMD’s Ex-pressFlash service), or both. CustomerLockable parts may utilize the SecSi Sector asbonus space, reading and writing like any otherflash sector, or may permanently lock their owncode there.
The device offers complete compatibility withthe JEDEC single-power-supply Flash com-mand set standard. Commands are written tothe command register using standard micro-processor write timings. Reading data out ofthe device is similar to reading from other Flashor EPROM devices.
The host system can detect whether a programor erase operation is complete by using the de-vice status bits: RY/BY# pin, DQ7 (Data# Poll-ing) and DQ6/DQ2 (toggle bits). After aprogram or erase cycle is completed, the deviceautomatically returns to the read mode. The sector erase architecture allows mem-ory sectors to be erased and reprogrammedwithout affecting the data contents of othersectors. The device is fully erased whenshipped from the factory.
Hardware data protection measures includea low VCC detector that automatically inhibitswrite operations during power transitions. Thehardware sector protection feature disablesboth program and erase operations in any com-bination of the sectors of memory. This can beachieved in-system or via programming equip-ment.
The device offers two power-saving features.When addresses are stable for a specifiedamount of time, the device enters the auto-matic sleep mode. The system can also placethe device into the standby mode. Power con-sumption is greatly reduced in both modes.
Am29LV320D Features
The SecSiTM Sector (Secured Silicon) is anextra sector capable of being permanentlylocked by AMD or customers. The SecSi Indi-cator Bit (DQ7) is permanently set to a 1 if thepart is factory locked, and set to a 0 if cus-tomer lockable. This way, customer lockableparts can never be used to replace a factorylocked part. Note that the Am29LV320D hasa SecSi Sector size of Kbytes. AMD de-vices designated as replacements or sub-stitutes, such as the Am29LV320M, have256 bytes. This should be considered dur-ing system design.
Factory locked parts provide several options.The SecSi Sector may store a secure, random16 byte ESN (Electronic Serial Number), cus-
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TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7Special Package Handling Instructions ....................................8Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Ordering Information . . . . . . . . . . . . . . . . . . . . . .10Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11
Table 1. Am29LV320D Device Bus Operations ..............................11
Figure 4. Program Operation......................................................... 27
Chip Erase Command Sequence ...........................................27Sector Erase Command Sequence ........................................27Erase Suspend/Erase Resume Commands ...........................28
Figure 5. Erase Operation.............................................................. 28
Command Definitions .............................................................29
Table 14. Am29LV320D Command Definitions .............................29
Write Operation Status . . . . . . . . . . . . . . . . . . . . 30DQ7: Data# Polling .................................................................30
Figure 6. Data# Polling Algorithm.................................................. 30
Word/Byte Configuration ........................................................11Requirements for Reading Array Data ...................................11Writing Commands/Command Sequences ............................12Accelerated Program Operation ..........................................12Autoselect Functions ...........................................................12Standby Mode ........................................................................12Automatic Sleep Mode ...........................................................13RESET#: Hardware Reset Pin ...............................................13Output Disable Mode ..............................................................13
Table 2. Top Boot Sector Addresses(Am29LV320DT) ..................13Table 3. Top Boot SecSiTM Sector Addresses................................ 14Table 4. Bottom Boot Sector Addresses(Am29LV320DB) .............15Table 5. Bottom Boot SecSiTM Sector Addresses.......................... 16
RY/BY#: Ready/Busy# ............................................................31DQ6: Toggle Bit I ....................................................................31
Figure 7. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ...................................................................32Reading Toggle Bits DQ6/DQ2 ...............................................32DQ5: Exceeded Timing Limits ................................................32DQ3: Sector Erase Timer .......................................................32
Table 15. Write Operation Status ...................................................33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 8. Maximum Negative OvershootWaveform...................... 34Figure 9. Maximum Positive OvershootWaveform........................ 34
Autoselect Mode .....................................................................16
Table 6. Autoselect Codes (HighVoltageMethod) ........................16
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. ICC1 Current vs. Time (Showing Active and
AutomaticSleepCurrents)............................................................. 36Figure 11. Typical ICC1 vs. Frequency............................................ 36
Sector/Sector Block Protection and Unprotection ..................17
Table 7. Top Boot Sector/Sector Block Addresses
forProtection/Unprotection .............................................................17Table 8. Bottom Boot Sector/Sector Block
AddressesforProtection/Unprotection ...........................................17
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Test Setup.................................................................... 37Table 16. Test Specifications .........................................................37Figure 13. Input Waveforms and Measurement Levels................. 37
Write Protect (WP#) ................................................................18Temporary Sector Unprotect ..................................................18
Figure 1. Temporary Sector Unprotect Operation........................... 18Figure 2. In-System Sector Protect/UnprotectAlgorithms.............. 19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. Read Operation Timings............................................... 38Figure 15. Reset Timings............................................................... 39
SecSiTM Sector (Secured Silicon) Flash Memory Region .......20Factory Locked: SecSi Sector Programmed
andProtectedattheFactory ...............................................20Customer Lockable: SecSi Sector NOT Programmed
orProtectedattheFactory ..................................................20
Figure 3. SecSi Sector Protect Verify.............................................. 21
Word/Byte Configuration (BYTE#) .............................................40
Figure 16. BYTE# Timings for Read Operations............................ 40Figure 17. BYTE# Timings for Write Operations............................ 40
Erase and Program Operations .................................................41
Figure 18. Program Operation Timings.......................................... 42Figure 19. Chip/Sector Erase Operation Timings.......................... 43Figure 20. Data# Polling Timings (DuringEmbeddedAlgorithms). 44Figure 21. Toggle Bit Timings (DuringEmbeddedAlgorithms)...... 45Figure 22. DQ2 vs. DQ6................................................................. 45
Hardware Data Protection ......................................................21Low VCC Write Inhibit .........................................................21Write Pulse “Glitch” Protection ............................................21Logical Inhibit ......................................................................21Power-Up Write Inhibit .........................................................21Common Flash Memory Interface (CFI) . . . . . . .21
Table 9. CFI Query Identification String.......................................... 22Table 10. System Interface String................................................... 22Table 11. Device Geometry Definition............................................ 23Table 12. Primary Vendor-Specific Extended Query...................... 24
Temporary Sector Unprotect .....................................................46
Figure 23. Temporary Sector Unprotect TimingDiagram.............. 46Figure 24. Accelerated Program Timing Diagram.......................... 46Figure 25. Sector/Sector Block Protect and
UnprotectTimingDiagram............................................................. 47
Alternate CE# Controlled Erase and ProgramOperations ........48
Figure 26. Alternate CE# Controlled Write
(Erase/Program)OperationTimings.............................................. 49
Command Definitions . . . . . . . . . . . . . . . . . . . . . .25Reading Array Data ................................................................25Reset Command .....................................................................25Autoselect Command Sequence ............................................25
Table 13. Autoselect Codes ............................................................25
Enter SecSiTM Sector/Exit SecSi Sector
CommandSequence ..............................................................26Byte/Word Program Command Sequence .............................26Unlock Bypass Command Sequence ..................................26
Erase And Programming Performance . . . . . . . 50Latchup Characteristics . . . . . . . . . . . . . . . . . . . 50TSOP and BGA Package Capacitance . . . . . . . . 50Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)
6x12mm package ...................................................................51TS 048—48-Pin Standard TSOP ...............................................52Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
5
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PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Max Access Time (ns)CE# Access (ns)OE# Access (ns)
Standard Voltage Range: VCC = 2.7–3.6 V
90R Standard Voltage Range: VCC = 3.0–3.6 V
Am29LV320D90
909040
120
12012050
BLOCK DIAGRAM
RY/BY#
VCCVSS
Sector SwitchesErase VoltageGenerator
Input/Output
BuffersDQ0–DQ15 (A-1)
RESET#
WE#BYTE#
StateControlCommandRegister
PGM VoltageGenerator
Chip EnableOutput Enable
Logic
STB
DataLatch
CE#OE#
STB
VCC Detector
Address LatchY-DecoderY-Gating
Timer
X-Decoder
Cell Matrix
A0–A20
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CONNECTION DIAGRAMS
A15A14A13A12A11A10A9A8A19A20WE#RESET#NCWP#/ACCRY/BY#A18A17A7A6A5A4A3A2A1123456710111213141516171819202122232448-Pin Standard TSOP4847454443424140393837363534333231302928272625A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0November 15, 2004Am29LV320D7
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CONNECTION DIAGRAMS
48-Ball FBGA
Top View, Balls Facing Down
A6A13A5A9A4WE#A3B6A12B5A8B4RESET#B3C6A14C5A10C4NCC3A18C2A6C1A2D6A15D5A11D4A19D3A20D2A5D1A1E6A16E5DQ7E4DQ5E3DQ2E2DQ0E1A0F6G6H6VSSH5DQ6H4DQ4H3DQ3H2DQ1H1VSSBYTE#DQ15/A-1F5DQ14F4DQ12F3DQ10F2DQ8F1CE#G5DQ13G4VCCG3DQ11G2DQ9G1OE#RY/BY#WP#/ACCA2A7A1A3B2A17B1A4Special Package Handling Instructions
Special handling is required for Flash Memoryproducts in molded (TSOP, BGA) packages.
The package and/or data integrity may be com-promised if the package body is exposed totemperatures above 150°C for prolonged peri-ods of time.
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PIN DESCRIPTION
A0–A20
=21 Addresses
DQ0–DQ14=15 Data Inputs/Outputs
DQ15/A-1=DQ15 (Data Input/Output, word
mode), A-1 (LSB Address Input, byte mode)CE#OE#WE#
=Chip Enable=Output Enable=Write Enable
LOGIC SYMBOL
21
A0–A2
DQ0–DQ15
(A-1)
CE# OE#WE#WP#/ACCRESET#BYTE#
RY/BY#
16 or 8
WP#/ACC=Hardware Write Protect/
Acceleration PinRESET#BYTE#RY/BY#VCC
=Hardware Reset Pin, Active Low=Selects 8-bit or 16-bit mode=Ready/Busy Output
=3.0 volt-only single power supply(see Product Selector Guide for speed
options and voltage supply toler-ances)=Device Ground
=Pin Not Connected Internally
VSSNC
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ORDERING INFORMATIONStandard Products
AMD standard products are available in several packages and operating ranges. The order number(Valid Combination) is formed by a combination of the following:
Am29LV32
0D
T
90
E
C
TEMPERATURE RANGEI Industrial (–40°C to +85°C)F Industrial (–40°C to +85°C) with Pb-free packageC Commercial (0°C to +70°C)D Commercial (0°C to +70°C) with Pb-free packageV=Automotive In-Cabin (-40°C to +105°C)Y=Automotive In-Cabin (-40°C to +105°C) with Pb-free packagePACKAGE TYPEE=48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
WM=48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 12 mm package (FBD048)SPEED OPTION
See Product Selector Guide and Valid CombinationsBOOT CODE SECTOR ARCHITECTURET=Top boot sectorB=Bottom boot sector
DEVICE NUMBER/DESCRIPTION
Am29LV320D
=32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Boot Sector Flash Memory=
3.0 Volt-only Read, Program and Erase=
=
Valid Combinations for TSOP Packages
AM29LV320DT90R,AM29LV320DB90RAm29LV320DT90,Am29LV320DB90AM29LV320DT120,AM29LV320DB120Am29LV320DT120Am29LV320DB120
EV, EYEC, EI,ED, EF
Speed(Ns)
9090120120
VCCRange
3.0– 3.6V2.7– 3.6V2.7– 3.6V2.7 – 3,6V
Valid Combinations for FBGA PackagesOrder NumberAM29LV320DT90,AM29LV320DB90AM29LV320DT120,AM29LV320DB120Am29LV320DT120Am29LV320DB120
WMC,WMI,WMD,WMFWNV
Package MarkingL320DT90V,L320DB90VL320DT12V,L320DB12VL320DT12VL320DB12V
C, I,D, F
V, Y
Valid Combinations
Valid Combinations list configurations planned to besupported in volume for this device. Consult the localAMD sales office to confirm availability of specificvalid combinations and to check on newly releasedcombinations.
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DEVICE BUS OPERATIONS
This section describes the requirements anduse of the device bus operations, which are ini-tiated through the internal command register.The command register itself does not occupyany addressable memory location. The registeris a latch used to store the commands, alongwith the address and data information neededto execute the command. The contents of the
Table 1.
register serve as inputs to the internal statemachine. The state machine outputs dictate thefunction of the device. Table 1 lists the devicebus operations, the inputs and control levelsthey require, and the resulting output. The fol-lowing subsections describe each of these oper-ations in further detail.
Am29LV320D Device Bus Operations
DQ8–DQ15
Operation
ReadWrite
Accelerated ProgramStandbyOutput DisableReset
Sector Protect (Note 2)Sector Unprotect (Note 2)
Temporary Sector Unprotect
CE#OE#
LLLVCC ± 0.3 VLXLLX
LHHXHXHHX
WE#
HLLXHXLLX
RESET#
HHHVCC ± 0.3 VHLVIDVIDVID
WP#/AC
C
L/H(Note 3)VHHHL/HL/HL/H(Note 3)(Note 3)
Addresses(Note 2)
AINAINAINXXX
DQ0–DQ7
DOUT
BYTE#= VIH
DOUT
BYTE# = VIL
DQ8–DQ14= High-Z, DQ15 = A-1High-ZHigh-ZHigh-ZXXHigh-Z
(Note 4)(Note 4)(Note 4)(Note 4)High-ZHigh-ZHigh-Z
High-ZHigh-ZHigh-ZXX
SA, A6 = L,
(Note 4)
A1 = H, A0 = L
SA, A6 = H,
(Note 4)
A1 = H, A0 = L
AIN
(Note 4)(Note 4)
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data OutNotes:
1.Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See
“Sector/Sector Block Protection and Unprotection” on page17.
3.If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot
sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection” on page17. If WP#/ACC = VHH, all sectors are unprotected.4.DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
Word/Byte Configuration
The BYTE# pin controls whether the devicedata I/O pins operate in the byte or word con-figuration. If the BYTE# pin is set at logic ‘1’,the device is in word configuration, DQ0–DQ15are active and controlled by CE# and OE#.If the BYTE# pin is set at logic ‘0’, the device isin byte configuration, and only data I/O pinsDQ0–DQ7 are active and controlled by CE# andOE#. The data I/O pins DQ8–DQ14 are
tri-stated, and the DQ15 pin is used as an inputfor the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the sys-tem must drive the CE# and OE# pins to VIL.CE# is the power control and selects the de-vice. OE# is the output control and gates arraydata to the output pins. WE# should remain atVIH. The BYTE# pin determines whether the de-vice outputs array data in words or bytes.
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The internal state machine is set for readingarray data upon device power-up, or after ahardware reset. This ensures that no spuriousalteration of the memory content occurs duringthe power transition. No command is necessaryin this mode to obtain array data. Standard mi-croprocessor read cycles that assert valid ad-dresses on the device address inputs producevalid data on the device data outputs. The de-vice remains enabled for read access until thecommand register contents are altered.
See “Requirements for Reading Array Data” onpage11 for more information. Refer to the ACRead-Only Operations table for timing specifi-cations and to Figure 14, on page 38 for thetiming diagram. ICC1 in the DC Characteristicstable represents the active current specificationfor reading array data.
This function is primarily intended to allowfaster manufacturing throughput at the factory. If the system asserts VHH on this pin, the deviceautomatically enters the aforementioned Un-lock Bypass mode, temporarily unprotects anyprotected sectors, and uses the higher voltageon the pin to reduce the time required for pro-gram operations. The system would use atwo-cycle program command sequence as re-quired by the Unlock Bypass mode. RemovingVHH from the WP#/ACC pin returns the deviceto normal operation. Note that the WP#/ACCpin must not be at VHH for operations otherthan accelerated programming, or device dam-age may result. In addition, the WP#/ACC pinmust not be left floating or unconnected; incon-sistent behavior of the device may result.Autoselect Functions
If the system writes the autoselect commandsequence, the device enters the autoselectmode. The system can then read autoselectcodes from the internal register (which is sepa-rate from the memory array) on DQ7–DQ0.Standard read cycle timings apply in this mode.Refer to the “Autoselect Mode” on page16 and“Autoselect Command Sequence” on page25sections for more information.
ICC6 and ICC7 in the DC Characteristics tablerepresent the current specifications forread-while-program and read-while-erase, re-spectively.
Writing Commands/Command Sequences
To write a command or command sequence(which includes programming data to the de-vice and erasing sectors of memory), the sys-tem must drive WE# and CE# to VIL, and OE#to VIH.
For program operations, the BYTE# pin deter-mines whether the device accepts programdata in bytes or words. Refer to “Word/ByteConfiguration” on page11 for more informa-tion.
The device features an Unlock Bypass modeto facilitate faster programming. Once the de-vice enters the Unlock Bypass mode, only twowrite cycles are required to program a word orbyte, instead of four. The “Word/Byte Configu-ration” on page11 section contains details onprogramming data to the device using bothstandard and Unlock Bypass command se-quences.
An erase operation can erase one sector, multi-ple sectors, or the entire device. Table2, onpage13 through Table5, on page16 indicatethe address space that each sector occupies. A“sector address” is the address bits required touniquely select a sector.
ICC2 in the DC Characteristics table representsthe active current specification for the writemode. The “AC Characteristics” on page38 sec-tion contains timing specification tables andtiming diagrams for write operations.Accelerated Program Operation
The device offers accelerated program opera-tions through the ACC function. This is one oftwo functions provided by the WP#/ACC pin.12
Standby Mode
When the system is not reading or writing tothe device, it can place the device in thestandby mode. In this mode, current consump-tion is greatly reduced, and the outputs areplaced in the high impedance state, indepen-dent of the OE# input.
The device enters the CMOS standby modewhen the CE# and RESET# pins are both heldat VCC ± 0.3 V. (Note that this is a more re-stricted voltage range than VIH.) If CE# and RE-SET# are held at VIH, but not within VCC ± 0.3V, the device is in the standby mode, but thestandby current is greater. The device requiresstandard access time (tCE) for read access whenthe device is in either of these standby modes,before it is ready to read data.
If the device is deselected during erasure orprogramming, the device draws active currentuntil the operation is completed.
ICC3 in the DC Characteristics table representsthe standby current specification.
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Automatic Sleep Mode
The automatic sleep mode minimizes Flash de-vice energy consumption. The device automati-cally enables this mode when addresses remainstable for tACC + 30ns. The automatic sleepmode is independent of the CE#, WE#, andOE# control signals. Standard address accesstimings provide new data when addresses arechanged. While in sleep mode, output data islatched and always available to the system. ICC4in the “DC Characteristics” on page35 tablerepresents the automatic sleep mode currentspecification.
(ICC4). If RESET# is held at VIL but not withinVSS±0.3 V, the standby current is greater.The RESET# pin may be tied to the systemreset circuitry. A system reset would thus alsoreset the Flash memory, enabling the system toread the boot-up firmware from the Flashmemory.
If RESET# is asserted during a program orerase operation, the RY/BY# pin remains a “0”(busy) until the internal reset operation is com-plete, which requires a time of tREADY (duringEmbedded Algorithms). The system can thusmonitor RY/BY# to determine whether thereset operation is complete. If RESET# is as-serted when a program or erase operation isnot executing (RY/BY# pin is “1”), the reset op-eration is completed within a time of tREADY (notduring Embedded Algorithms). The system canread data tRH after the RESET# pin returns toVIH.
Refer to the AC Characteristics tables for RE-SET# parameters and to Figure 15, on page 39for the timing diagram.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware methodof resetting the device to reading array data.When the RESET# pin is driven low for at leasta period of tRP, the device immediately termi-nates any operation in progress, tristates alloutput pins, and ignores all read/write com-mands for the duration of the RESET# pulse.The device also resets the internal state ma-chine to reading array data. The operation thatwas interrupted should be reinitiated once thedevice is ready to accept another command se-quence, to ensure data integrity.
Output Disable Mode
When the OE# input is at VIH, output from thedevice is disabled. The output pins are placed inthe high impedance state.
Current is reduced for the duration of the RE-SET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current
Table 2.Top Boot Sector Addresses(Am29LV320DT) (Sheet 1 of 2)
SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18Sector AddressA20–A12000000xxx000001xxx000010xxx000011xxx000100xxx000101xxx000110xxx000111xxx001000xxx001001xxx001010xxx001011xxx001100xxx001101xxx001110xxx001111xxx010000xxx010001xxx010010xxxSector Size(Kbytes/Kwords)
/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32(x8)Address Range000000h–00FFFFh010000h–01FFFFh020000h–02FFFFh030000h–03FFFFh040000h–04FFFFh050000h–05FFFFh060000h–06FFFFh070000h–07FFFFh080000h–08FFFFh090000h–09FFFFh0A0000h–0AFFFFh0B0000h–0BFFFFh0C0000h–0CFFFFh0D0000h–0DFFFFh0E0000h–0EFFFFh0F0000h–0FFFFFh100000h–10FFFFh110000h–11FFFFh120000h–12FFFFh(x16)Address Range000000h–07FFFh008000h–0FFFFh010000h–17FFFh018000h–01FFFFh020000h–027FFFh028000h–02FFFFh030000h–037FFFh038000h–03FFFFh040000h–047FFFh048000h–04FFFFh050000h–057FFFh058000h–05FFFFh060000h–067FFFh068000h–06FFFFh070000h–077FFFh078000h–07FFFFh080000h–087FFFh088000h–08FFFFh090000h–097FFFhNovember 15, 2004Am29LV320D13
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Table 2.
SectorSA19SA20SA21SA22SA23SA24SA25SA26SA27SA28SA29SA30SA31SA32SA33SA34SA35SA36SA37SA38SA39SA40SA41SA42SA43SA44SA45SA46SA47SA48SA49SA50SA51SA52SA53SA54SA55SA56SA57SA58SA59SA60SA61SA62SA63SASA65SA66SA67SA68SA69SA70Top Boot Sector Addresses(Am29LV320DT) (Sheet 2 of 2)
Sector Size(Kbytes/Kwords)
/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/328/48/48/48/48/48/48/48/4(x8)Address Range130000h–13FFFFh140000h–14FFFFh150000h–15FFFFh160000h–16FFFFh170000h–17FFFFh180000h–18FFFFh190000h–19FFFFh1A0000h–1AFFFFh1B0000h–1BFFFFh1C0000h–1CFFFFh1D0000h–1DFFFFh1E0000h–1EFFFFh1F0000h–1FFFFFh200000h–20FFFFh210000h–21FFFFh220000h–22FFFFh230000h–23FFFFh240000h–24FFFFh250000h–25FFFFh260000h–26FFFFh270000h–27FFFFh280000h–28FFFFh290000h–29FFFFh2A0000h–2AFFFFh2B0000h–2BFFFFh2C0000h–2CFFFFh2D0000h–2DFFFFh2E0000h–2EFFFFh2F0000h–2FFFFFh300000h–30FFFFh310000h–31FFFFh320000h–32FFFFh330000h–33FFFFh340000h–34FFFFh350000h–35FFFFh360000h–36FFFFh370000h–37FFFFh380000h–38FFFFh390000h–39FFFFh3A0000h–3AFFFFh3B0000h–3BFFFFh3C0000h–3CFFFFh3D0000h–3DFFFFh3E0000h–3EFFFFh3F0000h–3F1FFFh3F2000h–3F3FFFh3F4000h–3F5FFFh3F6000h–3F7FFFh3F8000h–3F9FFFh3FA000h–3FBFFFh3FC000h–3FDFFFh3FE000h–3FFFFFh(x16)Address Range098000h–09FFFFh0A0000h–0A7FFFh0A8000h–0AFFFFh0B0000h–0B7FFFh0B8000h–0BFFFFh0C0000h–0C7FFFh0C8000h–0CFFFFh0D0000h–0D7FFFh0D8000h–0DFFFFh0E0000h–0E7FFFh0E8000h–0EFFFFh0F0000h–0F7FFFh0F8000h–0FFFFFh100000h–107FFFh108000h–10FFFFh110000h–117FFFh118000h–11FFFFh120000h–127FFFh128000h–12FFFFh130000h–137FFFh138000h–13FFFFh140000h–147FFFh148000h–14FFFFh150000h–157FFFh158000h–15FFFFh160000h–167FFFh168000h–16FFFFh170000h–177FFFh178000h–17FFFFh180000h–187FFFh188000h–18FFFFh190000h–197FFFh198000h–19FFFFh1A0000h–1A7FFFh1A8000h–1AFFFFh1B0000h–1B7FFFh1B8000h–1BFFFFh1C0000h–1C7FFFh1C8000h–1CFFFFh1D0000h–1D7FFFh1D8000h–1DFFFFh1E0000h–1E7FFFh1E8000h–1EFFFFh1F0000h–1F7FFFh1F8000h–1F8FFFh1F9000h–1F9FFFh1FA000h–1FAFFFh1FB000h–1FBFFFh1FC000h–1FCFFFh1FD000h–1FDFFFh1FE000h–1FEFFFh1FF000h–1FFFFFhSector AddressA20–A12010011xxx010100xxx010101xxx010110xxx010111xxx011000xxx011001xxx011010xxx011011xxx011100xxx011101xxx011110xxx011111xxx100000xxx100001xxx100010xxx100011xxx100100xxx100101xxx100110xxx100111xxx101000xxx101001xxx101010xxx101011xxx101100xxx101101xxx101110xxx101111xxx110000xxx110001xxx110010xxx110011xxx110100xxx110101xxx110110xxx110111xxx111000xxx111001xxx111010xxx111011xxx111100xxx111101xxx111110xxx111111000111111001111111010111111011111111100111111101111111110111111111Note:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).
Table 3.
Sector Address A20–A12111111xxx Top Boot SecSiTM Sector Addresses
(x8)Address Range3F0000h–3FFFFFh(x16)Address Range1F8000h–1FFFFFh/32Sector Size(Kbytes/Kwords)
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Table 4.
SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19SA20SA21SA22SA23SA24SA25SA26SA27SA28SA29SA30SA31SA32SA33SA34SA35SA36SA37SA38SA39SA40SA41SA42SA43SA44SA45SA46SA47SA48SA49SA50SA51SA52Bottom Boot Sector Addresses(Am29LV320DB) (Sheet 1 of 2)
Sector Size(Kbytes/Kwords)
8/48/48/48/48/48/48/48/4/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32(x8)Address Range000000h-001FFFh002000h-003FFFh004000h-005FFFh006000h-007FFFh008000h-009FFFh00A000h-00BFFFh00C000h-00DFFFh00E000h-00FFFFh010000h-01FFFFh020000h-02FFFFh030000h-03FFFFh040000h-04FFFFh050000h-05FFFFh060000h-06FFFFh070000h-07FFFFh080000h-08FFFFh090000h-09FFFFh0A0000h-0AFFFFh0B0000h-0BFFFFh0C0000h-0CFFFFh0D0000h-0DFFFFh0E0000h-0EFFFFh0F0000h-0FFFFFh100000h-10FFFFh110000h-11FFFFh120000h-12FFFFh130000h-13FFFFh140000h-14FFFFh150000h-15FFFFh160000h-16FFFFh170000h-17FFFFh180000h-18FFFFh190000h-19FFFFh1A0000h-1AFFFFh1B0000h-1BFFFFh1C0000h-1CFFFFh1D0000h-1DFFFFh1E0000h-1EFFFFh1F0000h-1FFFFFh200000h-20FFFFh210000h-21FFFFh220000h-22FFFFh230000h-23FFFFh240000h-24FFFFh250000h-25FFFFh260000h-26FFFFh270000h-27FFFFh280000h-28FFFFh290000h-29FFFFh2A0000h-2AFFFFh2B0000h-2BFFFFh2C0000h-2CFFFFh2D0000h-2DFFFFh(x16)Address Range000000h–000FFFh001000h–001FFFh002000h–002FFFh003000h–003FFFh004000h–004FFFh005000h–005FFFh006000h–006FFFh007000h–007FFFh008000h–00FFFFh010000h–017FFFh018000h–01FFFFh020000h–027FFFh028000h–02FFFFh030000h–037FFFh038000h–03FFFFh040000h–047FFFh048000h–04FFFFh050000h–057FFFh058000h–05FFFFh060000h–067FFFh068000h–06FFFFh070000h–077FFFh078000h–07FFFFh080000h–087FFFh088000h–08FFFFh090000h–097FFFh098000h–09FFFFh0A0000h–0A7FFFh0A8000h–0AFFFFh0B0000h–0B7FFFh0B8000h–0BFFFFh0C0000h–0C7FFFh0C8000h–0CFFFFh0D0000h–0D7FFFh0D8000h–0DFFFFh0E0000h–0E7FFFh0E8000h–0EFFFFh0F0000h–0F7FFFh0F8000h–0FFFFFh100000h–107FFFh108000h–10FFFFh110000h–117FFFh118000h–11FFFFh120000h–127FFFh128000h–12FFFFh130000h–137FFFh138000h–13FFFFh140000h–147FFFh148000h–14FFFFh150000h–157FFFh158000h–15FFFFh160000h–167FFFh168000h–16FFFFhSector AddressA20–A12000000000000000001000000010000000011000000100000000101000000110000000111000001xxx000010xxx000011xxx000100xxx000101xxx000110xxx000111xxx001000xxx001001xxx001010xxx001011xxx001100xxx001101xxx001110xxx001111xxx010000xxx010001xxx010010xxx010011xxx010100xxx010101xxx010110xxx010111xxx011000xxx011001xxx011010xxx011011xxx011100xxx011101xxx011110xxx011111xxx100000xxx100001xxx100010xxx100011xxx100100xxx100101xxx100110xxx100111xxx101000xxx101001xxx101010xxx101011xxx101100xxx101101xxxNovember 15, 2004Am29LV320D15
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Table 4.
SectorSA53SA54SA55SA56SA57SA58SA59SA60SA61SA62SA63SASA65SA66SA67SA68SA69SA70Bottom Boot Sector Addresses(Am29LV320DB) (Sheet 2 of 2)
Sector Size(Kbytes/Kwords)
/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32(x8)Address Range2E0000h-2EFFFFh2F0000h-2FFFFFh300000h-30FFFFh310000h-31FFFFh320000h-32FFFFh330000h-33FFFFh340000h-34FFFFh350000h-35FFFFh360000h-36FFFFh370000h-37FFFFh380000h-38FFFFh390000h-39FFFFh3A0000h-3AFFFFh3B0000h-3BFFFFh3C0000h-3CFFFFh3D0000h-3DFFFFh3E0000h-3EFFFFh3F0000h-3FFFFFh(x16)Address Range170000h–177FFFh178000h–17FFFFh180000h–187FFFh188000h–18FFFFh190000h–197FFFh198000h–19FFFFh1A0000h–1A7FFFh1A8000h–1AFFFFh1B0000h–1B7FFFh1B8000h–1BFFFFh1C0000h–1C7FFFh1C8000h–1CFFFFh1D0000h–1D7FFFh1D8000h–1DFFFFh1E0000h–1E7FFFh1E8000h–1EFFFFh1F0000h–1F7FFFh1F8000h–1FFFFFhSector AddressA20–A12101110xxx101111xxx111000xxx110001xxx110010xxx110011xxx110100xxx110101xxx110110xxx110111xxx111000xxx111001xxx111010xxx111011xxx111100xxx111101xxx111110xxx111111xxxNote:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).
Table 5.
Sector Address
A20–A12000000xxx Bottom Boot SecSiTM Sector Addresses
Sector Size(Kbytes/Kwords)
/32(x8)
Address Range000000h-00FFFFh(x16)
Address Range00000h-07FFFhAutoselect Mode
The autoselect mode provides manufacturerand device identification, and sector protectionverification, through identifier codes output onDQ7–DQ0. This mode is primarily intended forprogramming equipment to automaticallymatch a device to be programmed with its cor-responding programming algorithm. However,the autoselect codes can also be accessedin-system through the command register.When using programming equipment, the au-toselect mode requires VID (11.5 V to 12.5 V)on address pin A9. Address pins A6, A1, and A0must be as shown in Table6, on page16. Inaddition, when verifying sector protection, the
Table 6.
Description
CE#
OE#
sector address must appear on the appropriatehighest order address bits (see Table2, onpage13 through Table5, on page16). Table6,on page16 shows the remaining address bitsthat are don’t care. When all necessary bits areset as required, the programming equipmentmay then read the corresponding identifiercode on DQ7–DQ0.
To access the autoselect codes in-system, thehost system can issue the autoselect commandvia the command register, as shown inTable14, on page29. This method does not re-quire VID. Refer to the “Autoselect CommandSequence” on page25 section for more infor-mation.
Autoselect Codes (HighVoltageMethod)
A20to A12XXSA
A11toA10XXX
A9
A8toA7XXX
A6
A5toA2XXX
DQ8 to DQ15
A1
A0
BYTE#BYTE# = VIH= VIL
X22hX
XXX
DQ7
toDQ001hF6 (T), F9h (B)01h (protected),00h (unprotected)99h (factory locked),19h (not factory
locked)
WE#
Manufacturer ID: AMDDevice ID: Am29LV320DSector Protection Verification
SecSiTM Sector Indicator Bit (DQ7)
LLL
LLL
HHH
VIDVIDVIDVID
LLL
LLH
LHL
LLHXXXLXHHXX
Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
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Sector/Sector Block Protection and Unprotection
The hardware sector protection feature disablesboth program and erase operations in any sec-tor. The hardware sector unprotection featurere-enables both program and erase operationsin previously protected sectors. Sector protec-tion/unprotection can be implemented via twomethods.
(Note: For the following discussion, the term“sector” applies to both sectors and sectorblocks. A sector block consists of two or moreadjacent sectors that are protected or unpro-tected at the same time (see Table7, onpage17 and Table8, on page17).
Table 7.Top Boot Sector/Sector Block Addresses forProtection/Unprotection
Sector / Sector
Block
SA0-SA3SA4-SA7SA8-SA11SA12-SA15SA16-SA19SA20-SA23SA24-SA27SA28-SA31SA32-SA35SA36-SA39SA40-SA43SA44-SA47SA48-SA51SA52-SA55SA56-SA59SA60-SA62
SA63SASA65SA66SA67SA68SA69SA70
A20–A12000000XXX,000001XXX,000010XXX000011XXX0001XXXXX0010XXXXX0011XXXXX0100XXXXX0101XXXXX0110XXXXX0111XXXXX1000XXXXX1001XXXXX1010XXXXX1011XXXXX1100XXXXX1101XXXXX1110XXXXX111100XXX,111101XXX,111110XXX111111000111111001111111010111111011111111100111111101111111110111111111
Sector/Sector Block
Size256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes192 (3x) Kbytes
8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes
SA7SA6SA5SA4SA3SA2SA1SA0
Table 8.Bottom Boot Sector/Sector Block AddressesforProtection/Unprotection
Sector / Sector
Block SA70-SA67SA66-SA63SA62-SA59SA58-SA55SA54-SA51SA50-SA47SA46-SA43SA42-SA39SA38-SA35SA34-SA31SA30-SA27SA26-SA23SA22–SA19SA18-SA15SA14-SA11SA10-SA8
A20–A12111111XXX,111110XXX,111101XXX,111100XXX1110XXXXX1101XXXXX1100XXXXX1011XXXXX1010XXXXX1001XXXXX1000XXXXX0111XXXXX0110XXXXX0101XXXXX0100XXXXX0011XXXXX0010XXXXX0001XXXXX000011XXX,000010XXX,000001XXX000000111000000110000000101000000100000000011000000010000000001000000000
Sector/Sector Block
Size256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes256 (4x) Kbytes192 (3x) Kbytes
8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes8 Kbytes
Sector Protection and unprotection requires VIDon the RESET# pin only, and can be imple-mented either in-system or via programmingequipment. Figure 2, on page 19 shows the al-gorithms and Figure 25, on page 47 shows thetiming diagram. This method uses standard mi-croprocessor bus cycle timing. For sector un-protect, all unprotected sectors must first beprotected prior to the first sector unprotectwrite cycle.
The sector unprotect algorithm unprotects allsectors in parallel. All previously protected sec-tors must be individually re-protected. Tochange data in protected sectors efficiently, thetemporary sector unprotect function is avail-able. See “Temporary Sector Unprotect” onpage18.
The alternate method intended only for pro-gramming equipment, and requires VID on ad-dress pin A9 and OE#. This method is
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compatible with programmer routines writtenfor earlier 3.0 volt-only AMD flash devices. Fordetailed information, contact an AMD represen-tative.
The device is shipped with all sectors unpro-tected. AMD offers the option of programmingand protecting sectors at its factory prior toshipping the device through AMD’s Express-Flash™ Service. Contact an AMD representativefor details.
It is possible to determine whether a sector isprotected or unprotected. See “AutoselectMode” on page16 for details.
23, on page 46 shows the timing diagrams, forthis feature.
START
RESET# = VID
(Note 1)Perform Erase or
Program
Write Protect (WP#)
The Write Protect function provides a hardwaremethod of protecting certain boot sectors with-out using VID. This function is one of two pro-vided by the WP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin,the device disables program and erase func-tions in the two “outermost” 8 Kbyte boot sec-tors independently of whether those sectorswere protected or unprotected using themethod described in “Sector/Sector Block Pro-tection and Unprotection” on page17. The twooutermost 8 Kbyte boot sectors are the twosectors containing the lowest addresses in abottom-boot-configured device, or the two sec-tors containing the highest addresses in atop-boot-configured device.
If the system asserts VIH on the WP#/ACC pin,the device reverts to whether the two outer-most 8K Byte boot sectors were last set to beprotected or unprotected. That is, sector pro-tection or unprotection for these two sectorsdepends on whether they were last protectedor unprotected using the method described in“Sector/Sector Block Protection and Unprotec-tion” on page17.
Note that the WP#/ACC pin must not be leftfloating or unconnected; inconsistent behaviorof the device may result.
RESET# = VIH
Temporary SectorUnprotect Completed
(Note 2)
Notes:
1.All protected sectors unprotected (If WP#/ACC =
VIL, outermost boot sectors remain protected).2.All previously protected sectors are protected
once again.
Figure 1.
Temporary Sector Unprotect
Operation
Temporary Sector Unprotect
This feature allows temporary unprotection ofpreviously protected sectors to change datain-system. The Sector Unprotect mode is acti-vated by setting the RESET# pin to VID (11.5 V– 12.5 V). During this mode, formerly pro-tected sectors can be programmed or erased byselecting the sector addresses. Once VID is re-moved from the RESET# pin, all the previouslyprotected sectors are protectedagain. Figure 1,on page 18 shows the algorithm, and Figure18
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STARTPLSCNT = 1RESET# = VIDWait 1 µsProtect all sectors:The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect addressSTARTPLSCNT = 1RESET# = VIDWait 1 µsTemporary SectorUnprotect ModeNoFirst Write Cycle = 60h?YesSet up sectoraddressSector Protect:Write 60h to sectoraddress withA6 = 0, A1 = 1, A0 = 0Wait 150 µsVerify Sector Protect: Write 40h to sector addresswith A6 = 0, A1 = 1, A0 = 0Read from sector addresswith A6 = 0, A1 = 1, A0 = 0NoNoFirst Write Cycle = 60h?YesAll sectorsprotected?YesSet up first sectoraddressSector Unprotect:Write 60h to sectoraddress withA6 = 1, A1 = 1, A0 = 0Temporary SectorUnprotect ModeIncrementPLSCNTResetPLSCNT = 1Wait 15 msVerify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0Read from sector addresswith A6 = 1, A1 = 1, A0 = 0Set upnext sectoraddressNoNoPLSCNT= 25?YesData = 01h?YesYesDevice failedProtect anothersector?NoRemove VID from RESET#Write reset commandIncrementPLSCNTNoNoPLSCNT= 1000?YesData = 00h?YesDevice failedLast sectorverified?YesNoSector ProtectAlgorithmSector ProtectcompleteSector UnprotectAlgorithmRemove VID from RESET#Write reset commandSector UnprotectcompleteFigure 2.In-System Sector Protect/UnprotectAlgorithms
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SecSiTM Sector (Secured Silicon) Flash Memory Region
The Secured Silicon Sector (SecSi Sector) fea-ture provides a Flash memory region that en-ables permanent part identification through anElectronic Serial Number (ESN). The SecSi Sec-tor uses a SecSi Sector Indicator Bit (DQ7) toindicate whether or not the SecSi Sector islocked when shipped from the factory. This bitis permanently set at the factory and cannot bechanged, which prevents cloning of a factorylocked part. This ensures the security of theESN once the product is shipped to the field.Note that the Am29LV320D has a SecSiSector size of Kbytes. AMD devices des-ignated as replacements or substitutes,such as the Am29LV320M, have 256 bytes.This should be considered during systemdesign.
AMD offers the device with the SecSi Sector ei-ther factory locked or customer lockable. Thefactory-locked version is always protectedwhen shipped from the factory, and has theSecSi Sector Indicator Bit permanently set to a“1.” The customer-lockable version is shippedwith the SecSi Sector unprotected, allowingcustomers to utilize the that sector in any man-ner they choose. The customer-lockable ver-sion has the SecSi Sector Indicator Bitpermanently set to a “0.” Thus, the SecSi Sec-tor Indicator Bit prevents customer-lockabledevices from being used to replace devices thatare factory locked.
The system accesses the SecSi Sector througha command sequence (see “Enter SecSiTM Sec-tor/Exit SecSi Sector CommandSequence” onpage26). After the system writes the EnterSecSi Sector command sequence, it may readthe SecSi Sector by using the addresses nor-mally occupied by the boot sectors. This modeof operation continues until the system issuesthe Exit SecSi Sector command sequence, oruntil power is removed from the device. Onpower-up, or following a hardware reset, thedevice reverts to sending commands to theboot sectors.
Factory Locked: SecSi Sector Programmed andProtectedattheFactory
In a factory locked device, the SecSi Sector isprotected when the device is shipped from thefactory. The SecSi Sector cannot be modified inany way. The device is available prepro-grammed with one of the following:■A random, secure ESN only
■Customer code through the ExpressFlashservice■Both a random, secure ESN and customercode through the ExpressFlash service.
In devices that have an ESN, a Bottom Boot de-vice has the 16-byte (8-word) ESN in sector 0at addresses 00000h–0000Fh in byte mode (or00000h–00007h in word mode). In the TopBoot device the ESN is in sector 63 at ad-dresses 3F0000h–3F000Fh in byte mode (or1F8000h–1F8007h in word mode). Note that inupcoming top boot versions of this device, theESN is located in sector 70 at addresses3FE000h–3FE00Fh in byte mode (or1FF000h–1FF007h in word mode).
Customers may opt to have their code pro-grammed by AMD through the AMD Express-Flash service. AMD programs the customer’scode, with or without the random ESN. The de-vices are then shipped from AMD’s factory withthe SecSi Sector permanently locked. Contactan AMD representative for details on usingAMD’s ExpressFlash service.
Customer Lockable: SecSi Sector NOT Programmed orProtectedattheFactoryThe customer lockable version allows the SecSiSector to be programmed once and then per-manently locked after it ships from AMD. Notethat the Am29LV320D has a SecSi Sectorsize of Kbytes. AMD devices designatedas replacements or substitutes, such asthe Am29LV320M, have 256 bytes. Thisshould be considered during system de-sign. Additionally, note the change in thelocation of the ESN in upcoming top bootfactory locked devices. Note that the accel-erated programming (ACC) and unlock bypassfunctions are not available when programmingthe SecSi Sector.
The SecSi Sector area can be protected usingthe following procedures:
■Write the three-cycle Enter SecSi Regioncommand sequence, and then follow thein-system sector protect algorithm as shownin Figure 2, on page 19, except that RESET#may be at either VIH or VID. This allowsin-system protection of the SecSi Sectorwithout raising any device pin to a high volt-age. Note that this method is only applicableto the SecSi Sector.■To verify the protect/unprotect status of theSecSi Sector, follow the algorithm shown inFigure 3, on page 21.
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Once the SecSi Sector is locked and verified,the system must write the Exit SecSi SectorRegion command sequence to return to readingand writing the remainder of the array.
The SecSi Sector protection must be used withcaution since, once protected, there is no pro-cedure available for unprotecting the SecSiSector area and none of the bits in the SecSiSector memory space can be modified in anyway.
until VCC is greater than VLKO. The system mustprovide the proper signals to the control pins toprevent unintentional writes when VCC isgreater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#,CE# or WE# do not initiate a write cycle.Logical Inhibit
Write cycles are inhibited by holding any one ofOE# = VIL, CE# = VIH or WE# = VIH. To initiatea write cycle, CE# and WE# must be a logicalzero while OE# is a logical one.Power-Up Write Inhibit
If data = 00h, SecSi Sector isunprotected.If data = 01h, SecSi Sector isprotected.STARTRESET# =VIH or VIDWait 1 µsWrite 60h to any addressIf WE# = CE# = VIL and OE# = VIH duringpower up, the device does not accept com-mands on the rising edge of WE#. The internalstate machine is automatically reset to the readmode on power-up.
Remove VIH or VID from RESET#Write reset commandSecSi SectorProtect VerifycompleteCOMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specificationoutlines device and host system software inter-rogation handshake, which allows specific ven-dor-specified software algorithms to be usedfor entire families of devices. Software supportcan then be device-independent, JEDEC ID-in-dependent, and forward- and backward-com-patible for the specified flash device families.Flash vendors can standardize their existing in-terfaces for long-term compatibility.
This device enters the CFI Query mode whenthe system writes the CFI Query command,98h, to address 55h in word mode (or addressAAh in byte mode), any time the device isready to read array data. The system can readCFI information at the addresses given inTable9, on page22 through Table12, onpage24. To terminate reading CFI data, thesystem must write the reset command. The system can also write the CFI query com-mand when the device is in the autoselectmode. The device enters the CFI query mode,and the system can read CFI data at the ad-dresses given in Table9, on page22 throughTable12, on page24. The system must writethe reset command to return the device to thereading array data.
For further information, please refer to the CFISpecification and CFI Publication 100, availablevia the World Wide Web athttp://www.amd.com/flash/cfi. Alternatively,contact an AMD representative for copies ofthese documents.
21
Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0Read from SecSi Sector addresswith A6 = 0, A1 = 1, A0 = 0Figure 3.SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlockcycles for programming or erasing providesdata protection against inadvertent writes (re-fer to Table14, on page29 for command defi-nitions). In addition, the following hardwaredata protection measures prevent accidentalerasure or programming, which might other-wise be caused by spurious system level signalsduring VCC power-up and power-down transi-tions, or from system noise.Low VCC Write Inhibit
When VCC is less than VLKO, the device does notaccept any write cycles. This protects data dur-ing VCC power-up and power-down. The com-mand register and all internal program/erasecircuits are disabled, and the device resets tothe read mode. Subsequent writes are ignoredNovember 15, 2004
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Table 9.
AddressesAddresses(Word Mode)(Byte Mode)
10h11h12h13h14h15h16h17h18h19h1Ah
20h22h24h26h28h2Ah2Ch2Eh30h32h34h
CFI Query Identification String
Description
Query Unique ASCII string “QRY”
Data
0051h0052h0059h0002h0000h0040h0000h0000h0000h0000h0000h
Primary OEM Command SetAddress for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
Table 10.
AddressesAddresses(Word Mode)(Byte Mode)
1Bh1Ch1Dh1Eh1Fh20h21h22h23h24h25h26h
36h38h3Ah3Ch3Eh40h42h44h46h48h4Ah4Ch
System Interface String
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present)VPP Max. voltage (00h = no VPP pin present)Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)Max. timeout for byte/word write 2N times typicalMax. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Data
0027h0036h0000h0000h0004h0000h000Ah0000h0005h0000h0004h0000h
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Table 11.
AddressesAddresses(Word Mode)(Byte Mode)
27h28h29h2Ah2Bh2Ch2Dh2Eh2Fh30h31h32h33h34h35h36h37h38h39h3Ah3Bh3Ch
4Eh50h52h54h56h58h5Ah5Ch5Eh60h62hh66h68h6Ah6Ch6Eh70h72h74h76h78h
Device Geometry Definition
Description
Device Size = 2N byte
Flash Device Interface description (refer to CFI publication 100)Max. number of bytes in multi-byte write = 2N (00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Data
0016h0002h0000h0000h0000h0002h0007h0000h0020h0000h003Eh0000h0000h0001h0000h0000h0000h0000h0000h0000h0000h0000h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
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Table 12.
AddressesAddresses(Word Mode)(Byte Mode)
40h41h42h43h44h45h
80h82h84h86h88h8Ah
Primary Vendor-Specific Extended Query
Data
0050h0052h0049h0031h0031h0000h
Description
Query-unique ASCII string “PRI”Major version number, ASCIIMinor version number, ASCIIAddress Sensitive Unlock (Bits 1-0)0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & WriteSector Protect
0 = Not Supported, X = Number of sectors in per groupSector Temporary Unprotect
00 = Not Supported, 01 = SupportedSector Protect/Unprotect scheme 04 = 29LV800 modeSimultaneous Operation00 = Not Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word PageACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mVACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mVTop/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
46h47h48h49h4Ah4Bh4Ch4Dh4Eh4Fh
8Ch8Eh90h92h94h96h98h9Ah9Ch9Eh
0002h0004h0001h0004h0000h0000h0000h00B5h00C5h000Xh
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COMMAND DEFINITIONS
Writing specific address and data commands orsequences into the command register initiatesdevice operations. Table14, on page29 definesthe valid register command sequences. Notethat writing incorrect address and data valuesor writing them in the improper sequence mayplace the device in an unknown state. A resetcommand is required to return the device tonormal operation.
All addresses are latched on the falling edge ofWE# or CE#, whichever happens later. All datais latched on the rising edge of WE# or CE#,whichever happens first. Refer to the AC Char-acteristics section for timing diagrams.
quence before programming begins. This resetsthe device to which the system was writing tothe read mode. If the program command se-quence is written to a sector that is in the EraseSuspend mode, writing the reset command re-turns the device to the erase-suspend-readmode. Once programming begins, however, thedevice ignores reset commands until the opera-tion is complete.
The reset command may be written betweenthe sequence cycles in an autoselect commandsequence. Once in the autoselect mode, thereset command must be written to return tothe read mode. If the device entered the au-toselect mode while in the Erase Suspendmode, writing the reset command returns thedevice to the erase-suspend-read mode.If DQ5 goes high during a program or erase op-eration, writing the reset command returns thedevice to the read mode (or erase-sus-pend-read mode if the device was in Erase Sus-pend).
Reading Array Data
The device is automatically set to reading arraydata after device power-up. No commands arerequired to retrieve data. The device is ready toread array data after completing an EmbeddedProgram or Embedded Erase algorithm.
After the device accepts an Erase Suspendcommand, the device enters the erase-sus-pend-read mode, after which the system canread data from any non-erase-suspended sec-tor. After completing a programming operationin the Erase Suspend mode, the system mayonce again read array data with the same ex-ception. See “Erase Suspend/Erase ResumeCommands” on page28 for more information.The system must issue the reset command toreturn the device to the read (or erase-sus-pend-read) mode if DQ5 goes high during anactive program or erase operation, or if the de-vice is in the autoselect mode. See the nextsection, “Reset Command, for more informa-tion.
See also “Requirements for Reading ArrayData” on page11 for more information. TheRead-Only Operations table provides the readparameters, and Figure 14, on page 38 showsthe timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows thehost system to read several identifier codes atspecific addresses:
Table 13.
Identifier CodeManufacturer ID
Device ID
SecSi Sector Factory ProtectSector Group Protect Verify
Autoselect Codes
Address00h01h03h(SA)02h
Reset Command
Writing the reset command resets the device tothe read or erase-suspend-read mode. Addressbits are don’t cares for this command.
The reset command may be written betweenthe sequence cycles in an erase command se-quence before erasing begins. This resets thedevice to which the system was writing to theread mode. Once erasure begins, however, thedevice ignores reset commands until the opera-tion is complete.
The reset command may be written betweenthe sequence cycles in a program command se-November 15, 2004
Table14, on page29 shows the address anddata requirements. This method is an alterna-tive to that shown in Table6, on page16,which is intended for PROM programmers andrequires VID on address pin A9. The autoselectcommand sequence may be written to an ad-dress within sector that is either in the read orerase-suspend-read mode. The autoselectcommand may not be written while the deviceis actively programming or erasing.
The autoselect command sequence is initiatedby first writing two unlock cycles. This is fol-lowed by a third write cycle that contains theautoselect command. The device then entersthe autoselect mode. The system may read atany address any number of times without initi-ating another autoselect command sequence.The system must write the reset command toreturn to the read mode (or erase-sus-pend-read mode if the device was previously inErase Suspend).
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Enter SecSiTM Sector/Exit SecSi Sector CommandSequence
The SecSi Sector region provides a secureddata area containing a random, sixteen-byteelectronic serial number (ESN). The system canaccess the SecSi Sector region by issuing thethree-cycle Enter SecSi Sector command se-quence. The device continues to access theSecSi Sector region until the system issues thefour-cycle Exit SecSi Sector command se-quence. The Exit SecSi Sector command se-quence returns the device to normal operation.Table14, on page29 shows the address anddata requirements for both command se-quences. Note that the ACC function and unlockbypass modes are not available when the de-vice enters the SecSi Sector. See also “SecSiTMSector (Secured Silicon) Flash Memory Region”on page20 for further information.
tempting to do so may cause the device to setDQ5 = 1, or cause the DQ7 and DQ6 status bitsto indicate the operation was successful. How-ever, a succeeding read shows that the data isstill “0.” Only erase operations can convert a“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system toprogram bytes or words to the device fasterthan using the standard program command se-quence. The unlock bypass command sequenceis initiated by first writing two unlock cycles.This is followed by a third write cycle containingthe unlock bypass command, 20h. The devicethen enters the unlock bypass mode. A two-cy-cle unlock bypass program command sequenceis all that is required to program in this mode.The first cycle in this sequence contains the un-lock bypass program command, A0h; the sec-ond cycle contains the program address anddata. Additional data is programmed in thesame manner. This mode dispenses with theinitial two unlock cycles required in the stan-dard program command sequence, resulting infaster total programming time. Table14, onpage29 shows the requirements for the com-mand sequence.
During the unlock bypass mode, only the Un-lock Bypass Program and Unlock Bypass Resetcommands are valid. To exit the unlock bypassmode, the system must issue the two-cycle un-lock bypass reset command sequence. The firstcycle must contain the data 90h. The secondcycle need only contain the data 00h. The de-vice then re turns to the read mode.
The device offers accelerated program opera-tions through the WP#/ACC pin. When the sys-tem asserts VHH on the WP#/ACC pin, thedevice automatically enters the Unlock Bypassmode. The system may then write the two-cy-cle Unlock Bypass program command se-quence. The device uses the higher voltage onthe WP#/ACC pin to accelerate the operation.Note that the WP#/ACC pin must not be at VHHany operation other than accelerated program-ming, or device damage may result. In addi-tion, the WP#/ACC pin must not be left floatingor unconnected; inconsistent behavior of thedevice may result.
Figure 4, on page 27 illustrates the algorithmfor the program operation. Refer to the table“Erase and Program Operations” on page41 forparameters, and Figure 18, on page 42 for tim-ing diagrams.
Byte/Word Program Command Sequence
The system may program the device by word orbyte, depending on the state of the BYTE# pin.Programming is a four-bus-cycle operation. Theprogram command sequence is initiated bywriting two unlock write cycles, followed by theprogram set-up command. The program ad-dress and data are written next, which in turninitiate the Embedded Program algorithm. Thesystem is not required to provide further con-trols or timings. The device automatically pro-vides internally generated program pulses andverifies the programmed cell margin. Table14,on page29 shows the address and data re-quirements for the byte program command se-quence. Note that the autoselect, SecSi Sector,and CFI modes are unavailable while a pro-gramming operation is in progress.
When the Embedded Program algorithm iscomplete, the device then returns to the readmode and addresses are no longer latched. Thesystem can determine the status of the pro-gram operation by using DQ7, DQ6, or RY/BY#.Refer to “Write Operation Status” on page30for information on these status bits.
Any commands written to the device during theEmbedded Program Algorithm are ignored.Note that a hardware reset immediately ter-minates the program operation. The programcommand sequence should be reinitiated oncethe device returns to the read mode, to ensuredata integrity.
Programming is allowed in any sequence andacross sector boundaries. A bit cannot beprogrammed from “0” back to a “1.” At-
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When the Embedded Erase algorithm is com-plete, the device returns to the read mode andaddresses are no longer latched. The systemcan determine the status of the erase operationby using DQ7, DQ6, DQ2, or RY/BY#. Refer to“Write Operation Status” on page30 for infor-mation on these status bits.
Any commands written during the chip eraseoperation are ignored. However, note that ahardware reset immediately terminates theerase operation. If that occurs, the chip erasecommand sequence should be reinitiated oncethe device returns to reading array data, to en-sure data integrity.
Figure 5, on page 28 illustrates the algorithmfor the erase operation. Refer to table “Eraseand Program Operations” on page41 for pa-rameters, and Figure 19, on page 43 section fortiming diagrams.
STARTWrite ProgramCommand SequenceEmbedded Programalgorithm in progressData Poll from SystemVerify Data?NoYesNoIncrement AddressLast Address?Sector Erase Command Sequence
Sector erase is a six bus cycle operation. Thesector erase command sequence is initiated bywriting two unlock cycles, followed by a set-upcommand. Two additional unlock cycles arewritten, and are then followed by the addressof the sector to be erased, and the sector erasecommand. Table14, on page29 shows the ad-dress and data requirements for the sectorerase command sequence. Note that the au-toselect, SecSi Sector, and CFI modes are un-available while an erase operation is inprogress.
The device does not require the system to pre-program prior to erase. The Embedded Erasealgorithm automatically programs and verifiesthe entire memory for an all zero data patternprior to electrical erase. The system is not re-quired to provide any controls or timings duringthese operations.
After the command sequence is written, a sec-tor erase time-out of 50 µs occurs. During thetime-out period, additional sector addressesand sector erase commands may be written.Loading the sector erase buffer may be done inany sequence, and the number of sectors maybe from one sector to all sectors. The time be-tween these additional cycles must be less than50µs, otherwise the last address and com-mand may not be accepted, and erasure maybegin. It is recommended that processor inter-rupts be disabled during this time to ensure allcommands are accepted. The interrupts can bere-enabled after the last Sector Erase com-mand is written. Any command other thanSector Erase or Erase Suspend during the
27
YesProgramming CompletedNote:See Table14, on page29 for program command sequence.
Figure 4.Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chiperase command sequence is initiated by writingtwo unlock cycles, followed by a set-up com-mand. Two additional unlock write cycles arethen followed by the chip erase command,which in turn invokes the Embedded Erase al-gorithm. The device does not require the sys-tem to preprogram prior to erase. TheEmbedded Erase algorithm automatically pre-programs and verifies the entire memory for anall zero data pattern prior to electrical erase.The system is not required to provide any con-trols or timings during these operations.Table14, on page29 shows the address anddata requirements for the chip erase commandsequence. Note that the autoselect, SecSi Sec-tor, and CFI modes are unavailable while anerase operation is in progress.
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time-out period resets the device to theread mode. The system must rewrite the com-mand sequence and any additional addressesand commands.
The system can monitor DQ3 to determine ifthe sector erase timer timed out (See the sec-tion “DQ3: Sector Erase Timer” on page32.).The time-out begins from the rising edge of thefinal WE# pulse in the command sequence.When the Embedded Erase algorithm is com-plete, the device returns to reading array dataand addresses are no longer latched. The sys-tem can determine the status of the erase op-eration by reading DQ7, DQ6, DQ2, or RY/BY#in the erasing sector. Refer to “Write OperationStatus” on page30 for information on thesestatus bits.
Once the sector erase operation begins, onlythe Erase Suspend command is valid. All othercommands are ignored. However, note that ahardware reset immediately terminates theerase operation. If that occurs, the sector erasecommand sequence should be reinitiated oncethe device returns to reading array data, to en-sure data integrity.
Figure 5, on page 28 illustrates the algorithmfor the erase operation. Refer to table “Eraseand Program Operations” on page41 for pa-rameters, and Figure 19, on page 43 for timingdiagrams.
pended sectors produces status information onDQ7–DQ0. The system can use DQ7, or DQ6and DQ2 together, to determine if a sector isactively erasing or is erase-suspended. Refer tothe “Write Operation Status” on page30 sec-tion for information on these status bits.After an erase-suspended program operation iscomplete, the device returns to the erase-sus-pend-read mode. The system can determinethe status of the program operation using theDQ7 or DQ6 status bits, just as in the standardByte Program operation. Referto “Write Opera-tion Status” on page30 for more information.In the erase-suspend-read mode, the systemcan also issue the autoselect command se-quence. Refer to “Autoselect Mode” on page16and “Autoselect Command Sequence” onpage25 for details.
To resume the sector erase operation, the sys-tem must write the Erase Resume command.Further writes of the Resume command are ig-nored. Another Erase Suspend command canbe written after the chip resumes erasing.
STARTErase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows thesystem to interrupt a sector erase operationand then read data from, or program data to,any sector not selected for erasure. This com-mand is valid only during the sector erase oper-ation, including the 50 µs time-out periodduring the sector erase command sequence.The Erase Suspend command is ignored if writ-ten during the chip erase operation or Embed-ded Program algorithm.
When the Erase Suspend command is writtenduring the sector erase operation, the devicerequires a maximum of 20 µs to suspend theerase operation. However, when the Erase Sus-pend command is written during the sectorerase time-out, the device immediately termi-nates the time-out period and suspends theerase operation.
After the erase operation is suspended, the de-vice enters the erase-suspend-read mode. Thesystem can read data from or program data toany sector not selected for erasure. (The device“erase suspends” all sectors selected for era-sure.) Reading at any address within erase-sus-28
Write Erase Command Sequence(Notes 1, 2)Data Poll to Erasing Bank from SystemNoEmbedded Erasealgorithmin progressData = FFh?YesErasure CompletedNotes:
1.See Table14, on page29 for erase command
sequence.2.See the section on DQ3 for information on the
sector erase timer.
Figure 5.Erase Operation
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Command Definitions
Table 14.
CyclesCommandSequence(Note 1)
Read (Note 6)Reset (Note 7)Manufacturer IDAutoselect (Note 8)Device ID SecSi Sector Factory Protect (Note 9)Sector Protect Verify (Note 10)
WordByteWordByteWordByteWord
4
ByteWordByteWordByteWordByteWordByte3443226611WordByte1
AAA555AAA555AAA555AAA555AAAXXXXXX555AAA555AAAXXXXXX55AAAAAAAAAAA090AAAAB03098
4
FirstRAXXX555AAA555AAA555AAA555
AA
5552AA5552AA5552AA5552AA555PAXXX2AA5552AA55555555555PD005555
555AAA555AAA8080
555AAA555AAAAAAA
2AA5552AA5555555
555AAASA
1030
AARDF0AAAA
2AA5552AA5552AA5552AA
55
AAA555AAA555AAA555AAA555AAA80A020
XXXPA
00PD
555555
555AAA555AAA555AAA555
90909090
X00X01X02X03X06(SA)X02(SA)X04
99/1901(see Table 6)
Am29LV320D Command Definitions
Bus Cycles (Notes 2–5)Second Third AddrDataFourth Fifth Sixth DataAddrDataAddrDataAddrDataAddrDataAddr1144
00/01
Enter SecSi™ Sector
Region
Exit SecSi Sector RegionProgramUnlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)Chip EraseSector Erase
Erase Suspend (Note 13)Erase Resume (Note 14)CFI Query (Note 15)
WordByteWordByteLegend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
Notes:
1.See Table 1 for description of bus operations.
2.3.4.5.6.7.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.
Unless otherwise noted, address bits A20–A11 are don’t cares.No unlock or command cycles required when device is in read mode.
The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information).
The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information.
The data is 99h for factory locked and 19h for not factory locked.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector.
8.
10.The data is 00h for an unprotected sector and 01h for a
protected sector.
11.The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12.The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
13.The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
14.The Erase Resume command is valid only during the Erase
Suspend mode.
15.Command is valid when device is ready to read array data or
when device is in autoselect mode.
9.
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WRITE OPERATION STATUS
The device provides several bits to determinethe status of a program or erase operation:DQ2, DQ3, DQ5, DQ6, and DQ7. Table15, onpage33 and the following subsections describethe function of these bits. DQ7 and DQ6 eachoffer a method for determining whether a pro-gram or erase operation is complete or inprogress. The device also provides a hard-ware-based output signal, RY/BY#, to deter-mine whether an Embedded Program or Eraseoperation is in progress or is completed.
when the system samples the DQ7 output, itmay read the status or valid data. Even if thedevice completes the program or erase opera-tion and DQ7 contains valid data, the data out-puts on DQ0–DQ6 may be still invalid. Validdata on DQ0–DQ7 appears on successive readcycles.
Table15, on page33 shows the outputs forData# Polling on DQ7. Figure 6, on page 30shows the Data# Polling algorithm. Figure 20,on page 44 in the AC Characteristics sectionshows the Data# Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to thehost system whether an Embedded Program orErase algorithm is in progress or completed, orwhether a device is in Erase Suspend. Data#Polling is valid after the rising edge of the finalWE# pulse in the command sequence.
During the Embedded Program algorithm, thedevice outputs on DQ7 the complement of thedatum programmed to DQ7. This DQ7 statusalso applies to programming during Erase Sus-pend. When the Embedded Program algorithmis complete, the device outputs the datum pro-grammed to DQ7. The system must provide theprogram address to read valid status informa-tion on DQ7. If a program address falls within aprotected sector, Data# Polling on DQ7 is activefor approximately 1 µs, then the device returnsto the read mode.
During the Embedded Erase algorithm, Data#Polling produces a “0” on DQ7. When the Em-bedded Erase algorithm is complete, or if thedevice enters the Erase Suspend mode, Data#Polling produces a “1” on DQ7. The systemmust provide an address within any of the sec-tors selected for erasure to read valid status in-formation on DQ7.
After an erase command sequence is written, ifall sectors selected for erasing are protected,Data# Polling on DQ7 is active for approxi-mately 100 µs, then the device returns to theread mode. If not all selected sectors are pro-tected, the Embedded Erase algorithm erasesthe unprotected sectors, and ignores the se-lected sectors that are protected. However, ifthe system reads DQ7 at an address within aprotected sector, the status may not be valid.Just prior to the completion of an EmbeddedProgram or Erase operation, DQ7 may changeasynchronously with DQ0–DQ6 while OutputEnable (OE#) is asserted low. That is, the de-vice may change from providing status infor-mation to valid data on DQ7. Depending on30
STARTRead DQ7–DQ0Addr = VADQ7 = Data?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Addr = VADQ7 = Data?YesNoFAILPASSNotes:
1.VA = Valid address for programming. During a
sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.2.DQ7 should be rechecked even if DQ5 = “1”
because DQ7 may change simultaneously with DQ5.
Figure 6.Data# Polling Algorithm
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RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain outputpin which indicates whether an Embedded Al-gorithm is in progress or complete. The RY/BY#status is valid after the rising edge of the finalWE# pulse in the command sequence. SinceRY/BY# is an open-drain output, severalRY/BY# pins can be tied together in parallelwith a pull-up resistor to VCC.
If the output is low (Busy), the device is ac-tively erasing or programming. (This includesprogramming in the Erase Suspend mode.) Ifthe output is high (Ready), the device is in theread mode, the standby mode, or in theerase-suspend-read mode. Table15, onpage33 shows the outputs for RY/BY#.
DQ6 also toggles during the erase-sus-pend-program mode, and stops toggling oncethe Embedded Program algorithm is complete.Table15, on page33 shows the outputs forToggle Bit I on DQ6. Figure 7, on page 31shows the toggle bit algorithm. Figure 21, onpage 45 in the “AC Characteristics” sectionshows the toggle bit timing diagrams. Figure22, on page 45 shows the differences betweenDQ2 and DQ6 in graphical form. See also thesubsection on DQ2: Toggle Bit II.
STARTDQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Em-bedded Program or Erase algorithm is inprogress or complete, or whether the deviceentered the Erase Suspend mode. Toggle Bit Imay be read at any address, and is valid afterthe rising edge of the final WE# pulse in thecommand sequence (prior to the program orerase operation), and during the sector erasetime-out.
During an Embedded Program or Erase algo-rithm operation, successive read cycles to anyaddress cause DQ6 to toggle. The system mayuse either OE# or CE# to control the read cy-cles. When the operation is complete, DQ6stops toggling.
After an erase command sequence is written, ifall sectors selected for erasing are protected,DQ6 toggles for approximately 100 µs, then re-turns to reading array data. If not all selectedsectors are protected, the Embedded Erase al-gorithm erases the unprotected sectors, and ig-nores the selected sectors that are protected. The system can use DQ6 and DQ2 together todetermine whether a sector is actively erasingor is erase-suspended. When the device is ac-tively erasing (that is, the Embedded Erase al-gorithm is in progress), DQ6 toggles. When thedevice enters the Erase Suspend mode, DQ6stops toggling. However, the system must alsouse DQ2 to determine which sectors are eras-ing or erase-suspended. Alternatively, the sys-tem can use DQ7 (see the subsection on “DQ7:Data# Polling” on page30).
If a program address falls within a protectedsector, DQ6 toggles for approximately 1 µsafter the program command sequence is writ-ten, then returns to reading array data.November 15, 2004
Read DQ7–DQ0Read DQ7–DQ0Toggle Bit = Toggle?YesNoNoDQ5 = 1?YesRead DQ7–DQ0TwiceToggle Bit = Toggle?YesProgram/EraseOperation Not Complete, Write Reset CommandNoProgram/EraseOperation CompleteNote:The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 7.
Am29LV320D
Toggle Bit Algorithm
31
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DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used withDQ6, indicates whether a particular sector isactively erasing (that is, the Embedded Erasealgorithm is in progress), or whether that sec-tor is erase-suspended. Toggle Bit II is validafter the rising edge of the final WE# pulse inthe command sequence.
DQ2 toggles when the system reads at ad-dresses within those sectors that were selectedfor erasure. (The system may use either OE#or CE# to control the read cycles.) But DQ2cannot distinguish whether the sector is ac-tively erasing or is erase-suspended. DQ6, bycomparison, indicates whether the device is ac-tively erasing, or is in Erase Suspend, but can-not distinguish which sectors are selected forerasure. Thus, both status bits are required forsector and mode information. Refer to Table15,on page33 to compare outputs for DQ2 andDQ6.
Figure 7, on page 31 shows the toggle bit algo-rithm in flowchart form, and the section “DQ2:Toggle Bit II” on page32 explains the algo-rithm. See also the DQ6: Toggle Bit I subsec-tion. Figure 21, on page 45 shows the toggle bittiming diagram. Figure 22, on page 45 showsthe differences between DQ2 and DQ6 ingraphical form.
write the reset command to return to readingarray data.
The remaining scenario is that the system ini-tially determines that the toggle bit is togglingand DQ5 has not gone high. The system maycontinue to monitor the toggle bit and DQ5through successive read cycles, determiningthe status as described in the previous para-graph. Alternatively, it may choose to performother system tasks. In this case, the systemmust start at the beginning of the algorithmwhen it returns to determine the status of theoperation (top of Figure 7, on page 31).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erasetime exceeded a specified internal pulse countlimit. Under these conditions DQ5 produces a“1,” indicating that the program or erase cyclewas not successfully completed.
The device may output a “1” on DQ5 if the sys-tem tries to program a “1” to a location thatwas previously programmed to “0.” Only anerase operation can change a “0” back to a“1.” Under this condition, the device halts theoperation, and when the timing limit is ex-ceeded, DQ5 produces a “1.”
Under both these conditions, the system mustwrite the reset command to return to the readmode (or to the erase-suspend-read mode ifthe device was previously in the erase-sus-pend-program mode).
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7, on page 31 for the followingdiscussion. Whenever the system initially be-gins reading toggle bit status, it must readDQ7–DQ0 at least twice in a row to determinewhether a toggle bit is toggling. Typically, thesystem would note and store the value of thetoggle bit after the first read. After the secondread, the system would compare the new valueof the toggle bit with the first. If the toggle bitis not toggling, the device completed the pro-gram or erase operation. The system can readarray data on DQ7–DQ0 on the following readcycle.
However, if after the initial two read cycles, thesystem determines that the toggle bit is stilltoggling, the system also should note whetherthe value of DQ5 is high (see the section onDQ5). If it is, the system should then deter-mine again whether the toggle bit is toggling,since the toggle bit may have stopped togglingjust as DQ5 went high. If the toggle bit is nolonger toggling, the device successfully com-pleted the program or erase operation. If it isstill toggling, the device did not completed theoperation successfully, and the system must32
DQ3: Sector Erase Timer
After writing a sector erase command se-quence, the system may read DQ3 to deter-mine whether or not erasure started. (Thesector erase timer does not apply to the chiperase command.) If additional sectors are se-lected for erasure, the entire time-out also ap-plies after each additional sector erasecommand. When the time-out period is com-plete, DQ3 switches from a “0” to a “1.” If thetime between additional sector erase com-mands from the system can be assumed to beless than 50 µs, the system need not monitorDQ3. See also the Sector Erase Command Se-quence section.
After the sector erase command is written, thesystem should read the status of DQ7 (Data#Polling) or DQ6 (Toggle Bit I) to ensure that thedevice accepted the command sequence, andthen read DQ3. If DQ3 is “1,” the EmbeddedErase algorithm started; all further commands(except Erase Suspend) are ignored until theerase operation is complete. If DQ3 is “0,” the
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device accepts additional sector erase com-mands. To ensure the command is accepted,the system software should check the status ofDQ3 prior to and following each subsequentsector erase command. If DQ3 is high on the
Table 15.
DQ7(Note 2)
DQ7#01DataDQ7#second status check, the last command mightnot have been accepted.
Table15, on page33 shows the status of DQ3relative to the other status bits.
Write Operation Status
DQ5(Note 1)
000Data0Status
Standard Embedded Program AlgorithmModeErase Suspend Mode
Embedded Erase AlgorithmErase Erase-Suspend-RSuspended Sector
eadNon-Erase Suspended SectorErase-Suspend-ProgramDQ6
ToggleToggleNo toggleDataToggleDQ3
N/A1N/ADataN/ADQ2(Note 2)
No toggleToggleToggleDataN/ARY/BY#
00110Notes:
1.DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum
timing limits. Refer to the section on DQ5 for more information.2.DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection
for further details.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages. . . . . . . . . .–65°C to +150°CAmbient Temperature
with Power Applied. . . . . . . .–65°C to +125°CVoltage with Respect to Ground
Notes:
1.Minimum DC voltage on input or I/O pins is –0.5
V. During voltage transitions, input or I/O pinsmay overshoot VSS to –2.0 V for periods of up to20 ns. Maximum DC voltage on input or I/O pinsis VCC +0.5 V. See Figure 8, on page 34. Duringvoltage transitions, input or I/O pins mayovershoot to VCC +2.0 V for periods up to 20 ns.See Figure 9, on page 34.2.Minimum DC input voltage on pins A9, OE#,
RESET#, and WP#/ACC is –0.5 V. During voltagetransitions, A9, OE#, WP#/ACC, and RESET#may overshoot VSS to –2.0 V for periods of up to20 ns. See Figure 8, on page 34. Maximum DCinput voltage on pin A9 is +12.5 V which mayovershoot to +14.0 V for periods up to 20 ns.Maximum DC input voltage on WP#/ACC is +9.5V which may overshoot to +12.0 V for periods upto 20 ns.3.No more than one output may be shorted to
ground at a time. Duration of the short circuitshould not be greater than one second.Stresses above those listed under “AbsoluteMaximum Ratings” may cause permanent damage tothe device. This is a stress rating only; functionaloperation of the device at these or any otherconditions above those indicated in the operationalsections of this data sheet is not implied. Exposureof the device to absolute maximum rating conditionsfor extended periods may affect device reliability.
VCC (Note 1) . . . . . . . . . .–0.5 V to +4.0 VA9, OE#, RESET#,
and WP#/ACC (Note 2). . –0.5 V to +12.5 VAll other pins (Note 1) –0.5 V to VCC +0.5 VOutput Short Circuit Current (Note 3). 200 mA
20 ns
+0.8VSS–0.5VSS–2.0
20 ns
20 ns
Figure 8.Maximum Negative
OvershootWaveform
20 ns
VCC+2.0VCC+0.5
2.0 V
20 ns
20 ns
Figure 9.Maximum Positive
OvershootWaveform
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA). . . .–40°C to +85°CVCC Supply Voltages
VCC for all devices . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which thefunctionality of the device is guaranteed.
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DC CHARACTERISTICSCMOS Compatible
Paramet
er Symbol
ILIILITILRILO
Parameter Description
Input Load CurrentA9 Input Load CurrentRESET# Input Load CurrentOutput Leakage Current
Test Conditions
VIN = VSS to VCC, VCC = VCC max
VCC = VCC max; A9 = 12.5 VVCC = VCC max; RESET# = 12.5 VVOUT = VSS to VCC, VCC = VCC max
CE# = VIL, OE# = VIH, Byte Mode
CE# = VIL, OE# = VIH, Word Mode
5 MHz1 MHz5 MHz1 MHz
MinTypMax
±3.03535±1.0
Unit
µAµAµAµA
102102150.20.20.2
–0.50.7 x VCC
16 416 4305550.8VCC + 0.312.5
mAµAµAµAVVVmA
ICC1
VCC Active Read Current (Notes 1, 2)
ICC2ICC3ICC4ICC5VILVIHVHHVIDVOLVOH1VOH2VLKO
VCC Active Write Current (Notes 2, 3)CE# = VIL, OE# = VIH, WE# = VILVCC Standby Current (Note 2)VCC Reset Current (Note 2)
Automatic Sleep Mode (Notes 2, 4)Input Low VoltageInput High Voltage
Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration
VCC = 3.0 V ± 10%
CE#, RESET# = VCC ± 0.3 VRESET# = VSS ± 0.3 VVIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V
11.5
Voltage for Autoselect and Temporary
VCC = 3.0 V ± 10%
Sector UnprotectOutput Low VoltageOutput High Voltage
Low VCC Lock-Out Voltage (Note 5)
11.512.5VVV
IOL = 4.0 mA, VCC = VCC min 0.45IOH = –2.0 mA, VCC = VCC min 0.85 VCCIOH = –100 µA, VCC = VCC min
VCC–0.42.3
2.5
V
Notes:
1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2.Maximum ICC specifications are tested with VCC = VCCmax.
3.ICC active while Embedded Erase or Embedded Program is in progress.
4.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep
mode current is 200 nA.5.Not 100% tested.
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DC CHARACTERISTICSZero-Power Flash
25Supply Current in mA20151050
0
500
1000
1500
2000Time in ns
Note:Addresses are switching at 1 MHz
2500300035004000
Figure 10.
ICC1 Current vs. Time (Showing Active and AutomaticSleepCurrents)
12
3.6 V
10
2.7 V
8Supply Current in mA6
4
2
01
Note:T = 25 °C
23
Frequency in MHz
45
Figure 11.
Typical ICC1 vs. Frequency
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TEST CONDITIONS
Table 16.
3.3 V
2.7 kΩ
Test Specifications
90
120
1 TTL gate 30
50.0–3.0
100
pFnsV
Test Condition
Output Load
Output Load Capacitance, CL(including jig capacitance)
Unit
DeviceUnderTest
CL
6.2 kΩ
Input Rise and Fall TimesInput Pulse Levels
Input timing measurement reference levels
Output timing measurement reference levels
1.5 V1.5
V
Note: Diodes are IN30 or equivalent
Figure 12. Test Setup
Key To Switching Waveforms
WAVEFORM
INPUTS
Steady
Changing from H to LChanging from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
OUTPUTS
3.0 V0.0 VInput1.5 VMeasurement Level1.5 VOutputFigure 13.Input Waveforms and Measurement Levels
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AC CHARACTERISTICSRead-Only Operations
ParameterJEDEC
tAVAVtAVQVtELQVtGLQVtEHQZtGHQZtAXQX
Speed Options
Description
Read Cycle Time (Note 1)Address to Output DelayChip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First
Read
Output Enable Hold Time
Toggle and (Note 1)
Data# Polling
CE#, OE# = VIL
OE# = VIL
Std.
tRCtACCtCEtOEtDFtDFtOH
Test Setup
MinMaxMaxMaxMaxMaxMinMinMin
90
90909040
16160010
120
12012012050
Unit
nsnsnsnsnsnsnsnsns
tOEH
Notes:
1.Not 100% tested.
2.See Figure 12, on page 37 and Table16, on page37 for test specifications.
tRCAddressesCE#Addresses StabletACCtRHtRHOE#tOEHWE#HIGH ZtCEtOHOutput ValidHIGH ZtOEtDFOutputsRESET#RY/BY#0 VFigure 14.Read Operation Timings
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AC CHARACTERISTICS
Hardware Reset (RESET#)
ParameterJEDEC
Std
tReadytReadytRPtRHtRPDtRB
Description
RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note)RESET# Pulse Width
Reset High Time Before Read (See Note)RESET# Low to Standby ModeRY/BY# Recovery Time
MaxMaxMinMinMinMin
All Speed Options
2050050050200
Unit
µsnsnsnsµsns
Note: Not 100% tested.
RY/BY#CE#, OE#tRHRESET#tRPtReadyReset Timings NOT during Embedded AlgorithmsReset Timings during Embedded AlgorithmstReadyRY/BY#tRBCE#, OE#tRHRESET#
tRPFigure 15.Reset Timings
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AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter JEDEC
Std.
tELFL/tELFHtFLQZtFHQV
Description
CE# to BYTE# Switching Low or HighBYTE# Switching Low to Output HIGH ZBYTE# Switching High to Output Active
MaxMax Min
90
51690
120Unit
nsns
120ns
CE#
OE#
BYTE#
tELFL
BYTE#Switching fromword to
bytemode
DQ0–DQ14
Data Output(DQ0–DQ14)DQ15OutputtFLQZ
Data OutputAddressInput
DQ15/A-1
tELFH
BYTE#
BYTE#Switching frombyte towordmode
DQ0–DQ14
Data OutputAddressInputtFHQ
Data Output(DQ0–DQ14)DQ15Output
DQ15/A-1
Figure 16.BYTE# Timings for Read Operations
CE#
The falling edge of the last WE#
WE#
BYTE#
tSET(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 17.BYTE# Timings for Write Operations
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AC CHARACTERISTICS
Erase and Program Operations
ParameterJEDEC
tAVAVtAVWL
Std.
tWCtAStASO
Description
Write Cycle Time (Note 1)Address Setup Time
Address Setup Time to OE# low during toggle bit polling Address Hold Time
Address Hold Time From CE# or OE# high during toggle bit pollingData Setup TimeData Hold Time
Output Enable High during toggle bit pollingRead Recovery Time Before Write (OE# High to WE# Low)CE# Setup TimeCE# Hold TimeWrite Pulse WidthWrite Pulse Width High
Latency Between Read and Write OperationsProgramming Operation (Note 2)Accelerated Programming Operation, Word or Byte (Note 2)
Sector Erase Operation (Note 2)VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#Program/Erase Valid to RY/BY# Delay
ByteWord
MinMinMinMinMinMinMinMinMinMinMinMinMinMinTypTypTypTypMinMinMax
90
90
01545
045
02000035
30091170.750090
120
120
Unit
nsnsns
tWLAXtAHtAHT
50nsns
tDVWHtWHDX
tDStDHtOEPH
50nsnsnsnsnsns
tGHWLtELWLtWHEHtWLWHtWHDL
tGHWLtCStCHtWPtWPHtSR/W
50nsnsnsµs
tWHWH1tWHWH1
tWHWH2
tWHWH1tWHWH1
tWHWH2tVCStRBtBUSY
µssecµsnsns
Notes:
1.Not 100% tested.
2.See “Erase And Programming Performance” on page50 for more information.
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AC CHARACTERISTICS
Program Command Sequence (last two cycles)tAStWCAddresses555hPAtAHCE#OE#tWPWE#tCStDSDatatDHPDtBUSYRY/BY#tVCSVCCStatusDOUTtRBtWPHtWHWH1Read Status Data (last two cycles)PAPAtCHA0hNotes:
1.PA = program address, PD = program data, DOUT is the true data at the program address.2.Illustration shows device in word mode.
Figure 18.Program Operation Timings
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AC CHARACTERISTICS
Erase Command Sequence (last two cycles)tWCAddresses2AAhtASSA555h for chip eraseRead Status DataVAtAHVACE#tCHtWPWE#tCStDStDHData55h30h10 for Chip EraseInProgressCompleteOE#tWPHtWHWH2tBUSYRY/BY#tVCSVCCtRBNotes:1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation
Status” on page30).2.These waveforms are for the word mode.
Figure 19.Chip/Sector Erase Operation Timings
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AC CHARACTERISTICS
tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ7ComplementComplementTrueValid DataHigh ZVAVAtCEtOEtDFDQ0–DQ6tBUSYRY/BY#Status DataStatus DataTrueValid DataHigh ZNote:VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 20.Data# Polling Timings (DuringEmbeddedAlgorithms)
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AC CHARACTERISTICS
tAHTAddressestAHTtASOCE#tOEHWE#tOEPHtCEPHtASOE#tDHDQ6/DQ2Valid DataValidStatustOEValidStatusValidStatusValid Data (first read)RY/BY#(second read)(stops toggling)Note:VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 21.Toggle Bit Timings (DuringEmbeddedAlgorithms)
EnterEmbeddedErasing
WE#
EraseSuspendEraseEnter EraseSuspend Program
EraseSuspendProgram
EraseResume
Erase Suspend
Read
Erase
EraseComplete
Erase SuspendRead
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 22.DQ2 vs. DQ6
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AC CHARACTERISTICS
Temporary Sector Unprotect
ParameterJEDEC
Std.
tVIDRtVHHtRSPtRRB
Description
VID Rise and Fall Time (See Note)VHH Rise and Fall Time (See Note)
RESET# Setup Time for Temporary Sector Unprotect
RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect
MinMinMinMin
All Speed Options
50025044
Unit
nsnsµsµs
Note: Not 100% tested.
VIDRESET#VSS, VIL,or VIHtVIDRProgram or Erase Command SequenceCE#tVIDRVIDVSS, VIL,or VIHWE#tRSPRY/BY#tRRB
Figure 23.Temporary Sector Unprotect TimingDiagram
VHHWP#/ACCVIL or VIHtVHHtVHHVIL or VIHFigure 24.Accelerated Program Timing Diagram
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AC CHARACTERISTICS
VIDVIHRESET#SA, A6,A1, A0Valid*Sector/Sector Block Protect or UnprotectValid*Verify40hSector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 msValid*Data60h60hStatus1 µsCE#WE#OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.Figure 25.Sector/Sector Block Protect and
UnprotectTimingDiagram
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AC CHARACTERISTICS
Alternate CE# Controlled Erase and ProgramOperations
ParameterJEDEC
tAVAVtAVWLtELAXtDVEHtEHDXtGHELtWLELtEHWHtELEHtEHELtWHWH1tWHWH1
tWHWH2
Std.
tWCtAStAHtDStDHtGHELtWStWHtCPtCPHtWHWH1tWHWH1tWHWH2
Description
Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time
Read Recovery Time Before Write (OE# High to WE# Low)WE# Setup TimeWE# Hold TimeCE# Pulse WidthCE# Pulse Width HighProgramming Operation (Note 2)
Accelerated Programming Operation, Word or Byte (Note 2)
Sector Erase Operation (Note 2)
ByteWord
MinMinMinMinMinMinMinMinMinMinTypTypTypTyp
90
90
04545
000045
3091170.7
120
120
Unit
nsns
5050
nsnsnsnsnsns
50nsnsµs
µssec
Notes:
1.Not 100% tested.
2.See “Erase And Programming Performance” on page50 for more information.
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AC CHARACTERISTICS
555 for program2AA for erase PA for programSA for sector erase555 for chip erase Data# PollingPAAddressestWCtWHWE#tGHELOE#tCPCE#tWStCPHtDStDHDatatRHA0 for program55 for erase PD for program30 for sector erase10 for chip erase tAStAHtWHWH1 or 2tBUSYDQ7#DOUTRESET#RY/BY#Notes:
1.Figure indicates last two bus cycles of a program or erase operation.
2.PA = program address, SA = sector address, PD = program data.
3.DQ7# is the complement of the data written to the device. DOUT is the data written to the device.4.Waveforms are for the word mode.
Figure 26.Alternate CE# Controlled Write (Erase/Program)OperationTimings
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ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase TimeChip Erase TimeByte Program TimeWord Program Time
Accelerated Byte/Word Program TimeChip Program Time (Note 3)
Byte ModeWord Mode
Typ (Note 1)Max (Note 2)
0.75091173624
300 3602101087215
Unit
secsecµsµsµssec
Comments
Excludes 00h programming prior to erasure (Note 4)
Excludes system level overhead (Note 5)
Notes:
1.Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles.
Additionally, programming typicals assume checkerboard pattern.2.Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3.The typical chip programming time is considerably less than the maximum chip programming time listed, since
most bytes program faster than the maximum program times listed.
4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before
erasure.
5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table14, on page29 for further information on command definitions.6.The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pinsVCC Current
Min
–1.0 V–1.0 V–100 mA
Max
12.5 VVCC + 1.0 V+100 mA
Note:Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND BGA PACKAGE CAPACITANCE
Parameter Symbol
CINCOUTCIN2
Parameter Description
Input CapacitanceOutput CapacitanceControl Pin Capacitance
Test Setup
VIN = 0VOUT = 0VIN = 0
TSOPFine-pitch BGA
TSOPFine-pitch BGA
TSOPFine-pitch BGA
Typ
.28.55.47.53.9
Max
7.55.0126.594.7
Unit
pFpFpFpFpFpF
Notes:
1.Sampled, not 100% tested.
2.Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Minimum Pattern Data Retention Time
Test Conditions
150°C125°C
Min
1020
Unit
YearsYears
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PHYSICAL DIMENSIONS
FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)6x12mm packageDwg rev AF; 1/2000xFBD 0486.00 mm x 12.00 mmPACKAGE1.200.200.940.8412.00 BSC6.00 BSC5.60 BSC4.00 BSC880.250.300.350.80 BSC0.40 BSCNovember 15, 2004Am29LV320D51
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PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOPDwg rev AA; 10/9952Am29LV320DNovember 15, 2004
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REVISION SUMMARY
Revision A (November 1, 2000)
Initial release.
Table 14, Am29LV320D Command DefinitionsCorrected autoselect codes for SecSi SectorFactory Protect.
Erase and Program Operations table
Corrected to indicate tBUSY specification is amaximum value.
Revision A+1 (January 23, 2001)
Ordering Information
Corrected FBGA part number table to includebottom boot part numbers.
Revision A+2 (February 1, 2001)
Connection DiagramsCorrected FBGA ball matrix.
Revision B+1 (July 30, 2002)
Figure 3, SecSi Sector Protect Verify
Deleted fifth block in flowchart and modifiedtext in fourth block.
Revision A+3 (July 2, 2001)
Global
Changed data sheet status from Advance Infor-mation to Preliminary.
Table 3, Top Boot SecSiTM Sector AddressesCorrected sector block size for SA60–SA62 to3x.
Sector/Sector Block Protection and Unprotection
Noted that sectors are erased in parallel.SecSiTM Sector (Secured Silicon) Flash Memory Region
Noted changes for upcoming versions of thesedevices: reduced SecSi Sector size, differentESN location for top boot devices, and deletionof SecSi Sector erase functionality. Current ver-sions of these devices remain unaffected.
Revision C (October 25, 2002)
Distinctive Characteristics
Changed endurance from “write” to “erase” cy-cles.
Connection Diagrams
Deleted ultrasonic reference and added pack-age types to special package handling text.Ordering Information
Added commercial temperature range and re-moved extended temperature range.SecSi Sector Flash Memory Region
Customer Lockable subsection: Deleted refer-ence to alternate method of sector protection.Command DefinitionsNoted the following:
Autoselect, SecSi Sector, and CFI functions arenot available during a program or erase opera-tion.
ACC and unlock bypass modes are not availablewhen the SecSi Sector is enabled.
Writing incorrect data or commands may placethe device in an unknown state. A reset com-mand is then required.AC Characteristics
Read-only Operations; Word/Byte Configura-tion: Changed tDF and tFLQZ to 16 ns for allspeed options.DC Characteristics
Deleted IACC and added ILR specifications fromtable.
TSOP, SO, and BGA Package CapacitanceAdded BGA capacitance to table.
Revision B (July 12, 2002)
Global
Deleted Preliminary status from document.Ordering InformationDeleted burn-in option.
Table 1, Am29LV320D Device Bus OperationsIn the legend, corrected VHH maximum voltageto 12.5 V.
SecSiTM Sector (Secured Silicon) Flash Memory Region
Added description of SecSi Sector protectionverification.
Autoselect Command SequenceClarified description of function.
November 15, 2004Am29LV320D53
元器件交易网www.cecb2b.com
Revision C+1 (February 16, 2003)
Distinctive Characteristics
Added reference to MirrorBit in Secured Silicon section.
Added Sector Architecture section.SecSi Sector Flash Memory Region
Referenced MirrorBit for an example in last sen-tence of first paragraph.Command Definitions
Changed the first address of the Unlock BypassReset from BA to XXX.
Erase and Programming Performance
Corrected the Sector Erase Time Typical to 0.7.
Ordering Information
Added Automotive In-Cabin temperature rangeand associated part numbers in the valid com-bination table.
Erase and Programming PerformanceUpdated Chip Erase TimeAC Characteristics
Added tRH line to Figure 15.
Erase and Program Operations
Corrected Sector Erase Operation timet
(WHWH2)
Alternate CE# Control Erase and Program Operations
Corrected Sector Erase Operation timet
(WHWH2)
Command Definitions
Update text in Sector Erase Command Se-quence paragraph.
Revision C+2 (April 4, 2003)
Distinctive Characteristics
Clarified reference to MirrorBit in Secured Sili-con section.
SecSi Sector Flash Memory Region
Clarified reference of MirrorBit for an examplein last sentence of first paragraph.
Revision C+3 (September 19, 2003)
Valid Combinations
Added the 90R package to table.
Revision C+4 (April 5, 2004)
Command Definitions
Changed first address data for Erase Sus-pend/Resume from BA to XXX.
Revision C+5 (June 4, 2004)
Ordering Information
Added Lead-free (Pb-free) options to the tem-perature ranges breakout table and valid com-binations table.Product Selector GuideAdded 90R voltage range.
Revision C+6 (November 15, 2004)
Global
Added ColophonUpdated TrademarksAdded reference links
54Am29LV320DNovember 15, 2004
元器件交易网www.cecb2b.com
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, includ-ing without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, de-veloped and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Adminis-tration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2000-2004 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective compa-nies.
November 15, 2004Am29LV320D55
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