DS90CF363A资料

DS90C363A/DS90CF363A+3.3VProgrammableLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-65MHz,+3.3VLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-65MHzJune1998

DS90C363A/DS90CF363A

+3.3VProgrammableLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-65MHz

+3.3VLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-65MHz

GeneralDescription

TheDS90C363A/DS90CF363Atransmitterconverts21bitsofCMOS/TTLdataintothreeLVDS(LowVoltageDifferentialSignaling)datastreams.Aphase-lockedtransmitclockistransmittedinparallelwiththedatastreamsoverafourthLVDSlink.Everycycleofthetransmitclock21bitsofinputdataaresampledandtransmitted.Atatransmitclockfre-quencyof65MHz,18bitsofRGBdataand3bitsofLCDtimingandcontroldata(FPLINE,FPFRAME,DRDY)aretransmittedatarateof455MbpsperLVDSdatachannel.Usinga65MHzclock,thedatathroughputis170Mbytes/sec.TheDS90C363AtransmittercanbeprogrammedforRisingedgestrobeorFallingedgestrobethroughadedi-catedpin.TheDS90CF363AisfixedasaFallingedgestrobetransmitter.ARisingedgeorFallingedgestrobetransmitterwillinteroperatewithaFallingedgestrobeRe-ceiver(DS90CF3)withoutanytranslationlogic.

ThischipsetisanidealmeanstosolveEMIandcablesizeproblemsassociatedwithwide,highspeedTTLinterfaces.

Features

n20to65MHzshiftclocksupport

nRejects>±3nsJitterfromVGAchipwithlessthan225psoutputJitter@65MHz(TJCC)

nBest–in–ClassSet&HoldTimesonTxINPUTsnTxpowerconsumption<130mW(typ)@65MHzGrayscale

n>50%LessPowerDissipationthanBiCMOSAlternatives

nTxPower-downmode<200µW(max)nESDrating>7kV(HBM),>500V(EIAJ)

nSupportsVGA,SVGA,XGAandDualPixelSXGA.nNarrowbusreducescablesizeandcostnUpto1.3Gbpsthroughput

nUpto170Megabytes/secbandwidth

n345mV(typ)swingLVDSdevicesforlowEMInPLLrequiresnoexternalcomponents

nCompatiblewithTIA/EIA-4LVDSstandardnLowprofile48-leadTSSOPpackagenImprovedreplacementfor:SN75LVDS85—DS90C363ASN75LVDS84—DS90CF363A

BlockDiagrams

DS90C363A/DS90CF363A

DS100138-1

OrderNumberDS90C363AMTDorDS90CF363AMTD

SeeNSPackageNumberMTD48

TRI-STATE®isaregisteredtrademarkofNationalSemiconductorCorporation.

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AbsoluteMaximumRatings(Note1)

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.

SupplyVoltage(VCC)−0.3Vto+4VCMOS/TTLInputVoltage−0.3Vto(VCC+0.3V)LVDSDriverOutputVoltage−0.3Vto(VCC+0.3V)LVDSOutputShortCircuitDurationContinuousJunctionTemperature+150˚CStorageTemperature−65˚Cto+150˚CLeadTemperature(Soldering,4sec)+260˚CMaximumPackagePowerDissipationCapacity@25˚CMTD48(TSSOP)Package:DS90C363A/DS90CF363A1.98WPackageDerating:

DS90C363A/DS90CF363A16mW/˚Cabove+25˚C

ESDRating

(HBM,1.5kΩ,100pF)(EIAJ,0Ω,200pF)

>7kV>500V

RecommendedOperatingConditions

SupplyVoltage(VCC)OperatingFreeAirTemperature(TA)ReceiverInputRange

SupplyNoiseVoltage(VCC)TxCLKINfrequency

Min3.0−10018

Nom3.3+25

Max3.6+702.410068

UnitsV˚CVmVPPMHz

ElectricalCharacteristics

Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.SymbolVIHVILVCLIINParameter

HighLevelInputVoltageLowLevelInputVoltageInputClampVoltageInputCurrent

ICL=−18mAVV

LVDSDCSPECIFICATIONSVOD∆VODVOS∆VOSIOSIOZDifferentialOutputVoltageChangeinVODbetweencomplimentaryoutputstatesOffsetVoltage(Note4)ChangeinVOSbetweencomplimentaryoutputstatesOutputShortCircuitCurrentOutput

TRI-STATE®

Current

VOUT=0V,RL=100ΩPowerDown=0V,VOUT=0VorVCCRL=100Ω,CL=5pF,

WorstCasePattern(Figures1,4)RL=100Ω,CL=5pF,

16GrayscalePattern(Figures2,4)f=32.5MHzf=37.5MHzf=65MHzf=32.5MHzf=37.5MHzf=65MHz

−3.5

1.125

1.25

RL=100Ω

250

345

450351.37535−5

mVmVVmVmAµA

ININConditionsMin2.0GND

TypMaxVCC0.8

UnitsVVVµAµA

CMOS/TTLDCSPECIFICATIONS

−0.79+1.8

−10

0

−1.5+10

=0.4V,2.5VorVCC=GND

±1±10

TRANSMITTERSUPPLYCURRENTICCTW

TransmitterSupplyCurrentWorstCase

31333923283310

43455235404555

mAmAmAmAmAmAµA

ICCTG

TransmitterSupplyCurrent16Grayscale

ICCTZ

TransmitterSupplyCurrentPowerDown

PowerDown=Low

DriverOutputsinTRI-STATE®underPowerDownMode

Note1:“AbsoluteMaximumRatings”arethosevaluesbeyondwhichthesafetyofthedevicecannotbeguaranteed.Theyarenotmeanttoimplythatthedeviceshouldbeoperatedattheselimits.Thetablesof“ElectricalCharacteristics”specifyconditionsfordeviceoperation.Note2:TypicalvaluesaregivenforVCC=3.3VandTA=+25C.

Note3:Currentintodevicepinsisdefinedaspositive.Currentoutofdevicepinsisdefinedasnegative.Voltagesarereferencedtogroundunlessotherwisespeci-fied(exceptVODand∆VOD).

Note4:VOSpreviouslyreferredasVCM.

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RecommendedTransmitterInputCharacteristics

OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolTCITTCIPTCIHTCIL

TxCLKINPeriod(Figure6)TxCLKINHighTime(Figure6)TxCLKINLowTime(Figure6)Parameter

TxCLKINTransitionTime(Figure5)14.70.35T0.35T

T0.5T0.5T

Min

Typ

Max555.60.65T0.65T

Unitsnsnsnsns

TransmitterSwitchingCharacteristics

OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolLLHTLHLTTPPos0TPPos1TPPos2TPPos3TPPos4TPPos5TPPos6TPPos0TPPos1TPPos2TPPos3TPPos4TPPos5TPPos6TPPos0TPPos1TPPos2TPPos3TPPos4TPPos5TPPos6TSTCTHTCTCCDTJCC

Parameter

LVDSLow-to-HighTransitionTime(Figure4)LVDSHigh-to-LowTransitionTime(Figure4)TransmitterOutputPulsePositionforBit0(Figure11)(Note5)TransmitterOutputPulsePositionforBit1TransmitterOutputPulsePositionforBit2TransmitterOutputPulsePositionforBit3TransmitterOutputPulsePositionforBit4TransmitterOutputPulsePositionforBit5TransmitterOutputPulsePositionforBit6

TransmitterOutputPulsePositionforBit0(Figure11)(Note5)TransmitterOutputPulsePositionforBit1TransmitterOutputPulsePositionforBit2TransmitterOutputPulsePositionforBit3TransmitterOutputPulsePositionforBit4TransmitterOutputPulsePositionforBit5TransmitterOutputPulsePositionforBit6

TransmitterOutputPulsePositionforBit0(Figure11)(Note5)TransmitterOutputPulsePositionforBit1TransmitterOutputPulsePositionforBit2TransmitterOutputPulsePositionforBit3TransmitterOutputPulsePositionforBit4TransmitterOutputPulsePositionforBit5TransmitterOutputPulsePositionforBit6TxINSetuptoTxCLKIN(Figure6)TxINHoldtoTxCLKIN(Figure6)TxCLKINtoTxCLKOUTDelay(Figure7)TA=25˚C,VCC=3.3VTxCLKINtoTxCLKOUTDelay(Figure7)TransmitterJitterCycle-to-Cycle(Figures12,13)(Note6)

f=65MHzf=40MHzf=32.5MHzf=32.5MHzf=40MHzf=65MHz

−0.301.904.106.308.5010.7012.90−0.353.226.7910.3613.9317.5121.08−0.404.008.4012.8017.2021.6026.002.5033

175240260

5.57.022538040010100

Min

Typ0.750.7502.204.406.608.8011.0013.2003.577.1410.7114.2817.8621.4304.408.8013.2017.6022.0026.40

Max1.51.50.202.404.606.809.0011.2013.400.353.927.4911.0614.6318.2121.780.404.809.2013.6018.0022.4026.80

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnspspspsmsns

TPLLSTPDD

TransmitterPhaseLockLoopSet(Figure8)TransmitterPowerDownDelay(Figure10)Note5:TheMinimumandMaximumLimitsarebasedonstatisticalanalysisofthedeviceperformanceoverprocess,voltage,andtemperatureranges.Thisparam-eterisfunctionalitytestedonlyonAutomaticTestEquipment(ATE).

Note6:TheLimitsarebasedonstatisticalanalysisofthedeviceperformanceoverprocess,voltage,andtemperatureranges.Outputjitterismeasuredwithacycle-to-cyclejitterof3nsappliedtotheinputclocksignal.Ajittereventof3ns,representsworsecasejumpintheclockedgefrommostGraphicscontrollerVGAchipscurrentlyavailable.Thisparameterisusedwhencalculatingsystemmargin(RSKM).SeeFigures12,13andAN-1059.

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ACTimingDiagrams

DS100138-4

FIGURE1.“WorstCase”TestPattern

DS100138-5

FIGURE2.“16Grayscale”TestPattern(Notes7,8,9,10)

Note7:Theworstcasetestpatternproducesamaximumtogglingofdigitalcircuits,LVDSI/OandCMOS/TTLI/O.

Note8:The16grayscaletestpatterntestsdevicepowerconsumptionfora“typical”LCDdisplaypattern.Thetestpatternapproximatessignalswitchingneededtoproducegroupsof16verticalstripesacrossthedisplay.

Note9:Figures1,2showafallingedgedatastrobe(TxCLKIN/RxCLKOUT).

Note10:Recommendedpintosignalmapping.Customermaychoosetodefinedifferently.

DS100138-30

FIGURE3.DS90C363A/DS90CF363A(Transmitter)LVDSOutputLoad

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ACTimingDiagrams

(Continued)

DS100138-6

FIGURE4.DS90C363A/DS90CF363A(Transmitter)LVDSTransitionTimes

DS100138-8

FIGURE5.DS90C363A/DS90CF363A(Transmitter)InputClockTransitionTime

DS100138-10

FIGURE6.DS90C363A/DS90CF363A(Transmitter)Setup/HoldandHigh/LowTimes(FallingEdgeStrobe)

DS100138-12

FIGURE7.DS90C363A/DS90CF363A(Transmitter)ClockIntoClockOutDelay(FallingEdgeStrobe)

DS100138-14

FIGURE8.DS90C363A/DS90CF363A(Transmitter)PhaseLockLoopSetTime

5

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ACTimingDiagrams

(Continued)

DS100138-17

FIGURE9.21ParallelTTLDataInputsMappedtoLVDSOutputs

DS100138-18

FIGURE10.TransmitterPowerDownDelay

DS100138-26

FIGURE11.TransmitterLVDSOutputPulsePositionMeasurement

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ACTimingDiagrams

(Continued)

DS100138-27

FIGURE12.TJCCTestSetup

DS100138-28

FIGURE13.TimingdiagramoftheInputcycle-to-cycleclockjitter

DS90C363APinDescription—FPDLinkTransmitter

PinNameTxINTxOUT+TxOUT−FPSHIFTINR_FBTxCLKOUT+TxCLKOUT−PWRDOWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND

I/OIOOIIOOIIIIIII

No.213311111341213

Description

TTLlevelinput.Thisincludes:6Red,6Green,6Blue,and3controllines—FPLINE,FPFRAMEandDRDY(alsoreferredtoasHSYNC,VSYNC,DataEnable).PositiveLVDSdifferentiaIdataoutput.NegativeLVDSdifferentialdataoutput.

TTLIevelclockinput.Thefallingedgeactsasdatastrobe.PinnameTxCLKIN.Programmablestrobeselect(SeeTable1).PositiveLVDSdifferentialclockoutput.NegativeLVDSdifferentialclockoutput.

TTLlevelinput.Whenasserted(lowinput)TRI-STATEStheoutputs,ensuringlowcurrentatpowerdown.

PowersupplypinsforTTLinputs.GroundpinsforTTLinputs.PowersupplypinforPLL.GroundpinsforPLL.

PowersupplypinforLVDSoutputs.GroundpinsforLVDSoutputs.

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DS90CF363APinDescription—FPDLinkTransmitter

PinNameTxINTxOUT+TxOUT−FPSHIFTINTxCLKOUT+TxCLKOUT−PWRDOWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND

I/OIOOIOOIIIIIII

No.21331111441213

Description

TTLlevelinput.Thisincludes:6Red,6Green,6Blue,and3controllines—FPLINE,FPFRAMEandDRDY(alsoreferredtoasHSYNC,VSYNC,DataEnable).PositiveLVDSdifferentialdataoutput.NegativeLVDSdifferentialdataoutput.

TTLIevelclockinput.Thefallingedgeactsasdatastrobe.PinnameTxCLKIN.PositiveLVDSdifferentialclockoutput.NegativeLVDSdifferentialclockoutput.

TTLlevelinput.Whenasserted(lowinput)TRI-STATEStheoutputs,ensuringlowcurrentatpowerdown.

PowersupplypinsforTTLinputs.GroundpinsforTTLinputs.PowersupplypinforPLL.GroundpinsforPLL.

PowersupplypinforLVDSoutputs.GroundpinsforLVDSoutputs.

ApplicationsInformation

TheDS90C363A/DS90CF363AarebackwardcompatiblewiththeDS90C363/DS90CF363andareapin-for-pinre-placement.Thedevice(DS90C363A/DS90CF363A)utilizesadifferentPLLarchitectureemployinganinternal7Xclockforenhancedpulsepositioncontrol.

Thisdevice(DS90C363A/DS90CF363A)alsofeaturesre-ducedvariationoftheTCCDparameterwhichisimportantfordualpixelapplications.(SeeAN-1084)TCCDvariationhasbeenmeasuredtobelessthan250psat65MHzundernormaloperatingconditions.

ThisdevicemayalsobeusedasareplacementfortheDS90CF563(5V,65MHz)andDS90CF561(5V,40MHz)FPD-LinkTransmitterswithcertainconsiderations/modifications:

1.2.

Change5Vpowersupplyto3.3V.ProvidethissupplytotheVCC,LVDSVCCandPLLVCCofthetransmitter.TheDS90C363Atransmitterinputandcontrolinputsac-cept3.3VTTL/CMOSlevels.Theyarenot5Vtolerant.3.ToimplementafallingedgedevicefortheDS90C363A,

theR_FBpin(pin14)maybetiedtogroundORleftun-connected(aninternalpull-downresistorbiasesthispinlow).BiasingthispintoVccimplementsarisingedgedevice.

TransmitterClockJitterCycle-to-Cycle

Figures12and13illustratethetimingoftheinputclockrela-tivetotheinputdata.Theinputclock(TxCLKin)isintention-allyshiftedtotheleft−3nsand+3nstotherightwhendata(Txin0-27)ishigh.This3nsofcycle-to-cycleclockjitterisre-peatedataperiodof2µs,whichistheperiodoftheinputdata(1µshigh,1µslow).AtdifferentoperatingfrequenciestheNCycleischangedtomaintainthedesired3nscycle-to-cyclejitterat2µsperiod.

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PinDiagram

DS90C363A

DS90CF363A

DS100138-23DS100138-24

Application

DS100138-3

TruthTable

TABLE1.ProgrammableTransmitter(DS90C363A)PinR_FBR_FB

ConditionR_FB=VCCR_FB=GNDorNC

StrobeStatusRisingedgestrobeFallingedgestrobe

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DS90C363A/DS90CF363A+3.3VProgrammableLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-65MHz,+3.3VLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-65MHzPhysicalDimensions

inches(millimeters)unlessotherwisenoted

48-LeadMoldedThinShrinkSmallOutlinePackage,JEDEC

OrderNumberDS90C363AMTD,DS90CF363AMTD

NSPackageNumberMTD48

LIFESUPPORTPOLICY

NATIONAL’SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDE-VICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFTHEPRESIDENTOFNATIONALSEMI-CONDUCTORCORPORATION.Asusedherein:

2.Acriticalcomponentinanycomponentofalifesupport1.Lifesupportdevicesorsystemsaredevicesorsys-deviceorsystemwhosefailuretoperformcanberea-temswhich,(a)areintendedforsurgicalimplantinto

sonablyexpectedtocausethefailureofthelifesupportthebody,or(b)supportorsustainlife,andwhosefail-deviceorsystem,ortoaffectitssafetyoreffectiveness.uretoperformwhenproperlyusedinaccordance

withinstructionsforuseprovidedinthelabeling,canbereasonablyexpectedtoresultinasignificantinjurytotheuser.

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