CY2CC910_08资料

CY2CC910

1:10 Clock Fanout Buffer

Features

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Description

The Cypress series of network circuits are produced usingadvanced 0.35 micron CMOS technology, achieving theindustry’s fastest logic and buffers.

The Cypress CY2CC910 fanout buffer features one input and10 outputs. It is ideal for conversion from and to 3.3V, 2.5V,and 1.8V

Designed for Data Communications clock management appli-cations, the large fanout from a single input reduces loadingon the input clock.

Cypress employs the unique AVCMOS type outputs VOI(Variable Output Impedance) that dynamically adjust forvariable impedance matching, eliminate the need for seriesdamping resistors, and reduce overall noise.

Low voltage operationFull range support: ❐3.3V❐2.5V❐1.8V

Over voltage tolerant input hot swappable1:10 Fanout

Drives either a 50-Ohm or 75-Ohm loadLow input capacitanceLow output skewLow propagation delayTypical (tpd less than 4 ns)High speed operation:❐200 MHz at1.8V

❐650 MHz at 2.5V and 3.3VIndustrial versions available

Available packages include: SOIC, SSOP

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Logic Block Diagram3Q15Q2Q3Q4Q5Q6Q7Q8Q9Q10OUTPUT(AVCMOS)VDD4,815,20IN17911INPUT(AVCMOS)2,6,1013,171214GND161819CypressSemiconductorCorporationDocument #: 38-07348 Rev. *C

•198 Champion Court•

SanJose,CA95134-1709•408-943-2600

Revised October 22, 2008

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CY2CC910

Pin Configuration

Figure 1. 20-Pin SOIP-SSOP

INGNDQ1VDDQ2GNDQ3VDDQ4GND12345671020191817161514131211VDDQ10Q9GNDQ8VDDQ7GNDQ6Q520 pin SOIC/SSOPPin Description

Pin Number

1

2,6,10,13,174,8,15,20

3,5,7,9,11,12,14,16,18,19

IN

Pin Name

InputGroundPower SupplyOutput

Description

GNDVDD

Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10

Maximum Ratings[1]

Storage Temperature:.................................–65°C to +150°CAmbient Temperature:..................................–40°C to +85°CSupply Voltage to Ground Potential

VCC...................................................................–0.5V to 4.6VInput..................................................................–0.5V to 5.8V

Supply Voltage to Ground Potential

(Outputs only)...........................................–0.5V to VDD + 1VDC Output Voltage....................................–0.5V to VDD + 1VPower Dissipation........................................................0.75W

Note

1.Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Document #: 38-07348 Rev. *C

CY2CC910Page 2 of 11

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CY2CC910

Variable Output Impedance Control (VOI)

Figure 2. Output Voltage versus Output Current (TA = 25°C) Pull Down3.5Pull Up3.5332.52.5221.51.5110.50.5000.010.020.030.040.050.060.070.080.090.10-0.18-0.16-0.14-0.12-0.1-0.08-0.06-0.04-0.020Iol (A)Vdd = 3.3 VVdd = 2.5 VVdd = 1.8 VVdd = 3.3 VIoh (A)Vdd = 2.5 VVdd = 1.8 VDC Electrical Characteristics

At 3.3V (See Figure3)

ParameterVOHVOLVIHVILIIHIILIIVIKIOKOOFFVH

Description

Output High VoltageOutput Low VoltageInput High VoltageInput Low VoltageInput High Current Input Low CurrentInput High CurrentClamp Diode VoltageContinuous Clamp CurrentPower-down DisableInput Hysteresis

Conditions

VDD = Min., VIN = VIH or VILIOH = –12 mAVDD = Min., VIN = VIH or VILIOL = 12 mAGuaranteed Logic High Level

Guaranteed Logic Low LevelVDD = Max.VDD = Max.

VDD = Max., VIN = VDD(Max.)VDD = Min., IIN = –18 mAVDD = Max., VOUT = GNDVDD = GND, VOUT = < 4.5V

80–0.7

VIN = 2.7VVIN = 0.5V

Min2.32

Typ3.30.2

0.55.80.81–120–1.2–50100Max

UnitVVVVμAμAμAVmAμAmV

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CY2CC910

At 2.5V (See Figure3)

ParameterVOHVOLVIHVILIIHIILIIVIKIOKOOFFVH

Description

Output High VoltageOutput Low VoltageInput High VoltageInput Low VoltageInput High Current Input Low CurrentInput High CurrentClamp Diode VoltageContinuous Clamp CurrentPower Down DisableInput Hysteresis

Conditions

VDD = Min., VIN = VIH or VILVDD = Min., VIN = VIH or VILGuaranteed Logic High LevelGuaranteed Logic Low LevelVDD = Max.VDD = Max.

VDD = Max., VIN = VDD(Max.)VDD = Min., IIN = –18 mAVDD = Max., VOUT = GNDVDD = GND, VOUT = < 4.5V

80–0.7

VIN = 2.4VVIN = 0.5VIOH = –7 mAIOH = 12 mAIOL = 12 mA

1.6Min1.81.6

0.655.00.81–120–1.2–50100

Typ

Max

UnitVVVVVμAμAμAVmAμAmV

At 1.8V (See Figure7)

ParameterVDDVIHVILVOHVOL

Description

Supply VoltageInput High VoltageInput Low VoltageOutput High VoltageOutput Low Voltage

IOH = –2 mAIOH = 2 mA

Test Condition[2]Min1.710.65VDD[1.1]

–0.3VDD – 0.45[1.2]

0.45Max1.4.30.35 VDD[0.6]

UnitVVVVV

Capacitance

ParameterCINCOUT

Description

Input CapacitanceOutput Capacitance

VIN = 0VVOUT = 0V

Test Conditions

Typ2.56.5

Max

UnitpFpF

Power Supply Characteristics (See Figure3)

ParameterΔICCICCDIC

Description

Delta ICC Quiescent Power Supply CurrentDynamic Power Supply Current

Total Power Supply Current

Test Conditions

(IDD @ VDD = Max and VIN = VDD) – (IDD @ VDD = Max and VIN = VDD – 0.6V)VDD = Max

Input toggling 50% Duty Cycle, Outputs Open

VDD = Max

Input toggling 50% Duty

Cycle, Outputs Open fL = 40 MHZ

Min

Typ

Max500.63

UnitμAmA/MHzmA

25

Note

2.Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency.

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CY2CC910

High Frequency Parametrics

ParameterDJFmax3.3V

DescriptionJitter, Deterministic

Test Conditions

50% duty cycle tW(50–50) The “point to point load circuit”| Output Jitter – Input Jitter |50% duty cycle tW(50–50)Standard Load Circuit.50% duty cycle tW(50–50)

The “point to point load circuit”

Fmax2.5VFmax1.8VFmax(20)

Maximum frequency VDD = 2.5VMaximum frequencyVDD = 1.8VMaximum frequencyVDD = 3.3VMinimum pulseVDD = 3.3V Minimum pulseVDD = 2.5VMinimum pulseVDD = 1.8V

The “point-to-point load circuit”VIN = 2.4V/0.0V VOUT = 1.7V/0.7VThe “6-pF load circuit”

VIN = 1.7/0.0V VOUT = 1.2V/0.4V20% duty cycle tW(20-80)

The “point to point load circuit”VIN = 3.0V/0.0V VOUT = 2.3V/0.4VThe “point-to-point load circuit”VIN = 3.0V/0.0V F = 100 MHzVOUT = 2.0V/0.8V

The “point-to-point load circuit”VIN = 2.4V/0.0V F = 100 MHzVOUT = 1.7V/0.7V

The “6-pF load circuit”

VIN = 1.7V/0.0V VOUT = 1.2V/0.4V

See Figure5

Min

Typ

Max20

Unitps

Maximum frequencyVDD = 3.3V

See Figure3See Figure5See Figure5See Figure7See Figure6

160650200200250

MHz

MHzMHzMHz

tW3.3VtW2.5VtW1.8V

See Figure51ns

See Figure51ns

See Figure71ns

AC Switching Characteristics

At 3.3V (VDD = 3.3V ± 5%, Temperature = –40°C to +85°C)ParametertPLHtPHLtRtFtSK(0)tSK(p)tSK(t)

Propagation Delay – Low to HighPropagation Delay – High to LowOutput Rise TimeOutput Fall Time

Output Skew: Skew between outputs of the same package (in phase).

Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH).

See Figure11See Figure10

Description

See Figure4

Min1.51.5

Typ2.72.70.80.8

0.20.20.4Max3.53.5

UnitnsnsV/nsV/nsnsnsns

Package Skew: Skew between outputs of different packages at See Figure12the same power supply voltage, temperature and package type.

At 2.5V (VDD = 2.5V ± 5%, Temperature = –40°C to +85°C)ParametertPLHtPHLtRtFtSK(0)tSK(p)tSK(t)

Propagation Delay – Low to HighPropagation Delay – High to LowOutput Rise TimeOutput Fall Time

Output Skew: Skew between outputs of the same package (in phase).

See Figure11

Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure10– tPLH).

Package Skew: Skew between outputs of different packages at the same See Figure12power supply voltage, temperature and package type.

Description

Min

See Figure4 1.51.5

Typ2.72.70.80.8

0.20.20.4MaxUnit3.53.5

nsnsV/nsV/nsnsnsns

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CY2CC910

AC Switching Characteristics

At 1.8V(VDD = 1.8V ±5%, Temperature = –40°C to +85°C)ParametertPLHtPHLtRtFtSK(0)tSK(p)tSK(t)

DescriptionPropagation Delay – Low to HighPropagation Delay – High to LowOutput Rise Time 20 – 80%Output Fall Time 20 – 80%Output Skew: Skew between outputs of the same package (in phase).Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH).

Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type.

See Figure8

Min1.51.50.20.2TypMaxUnit2.73.5ns2.73.5ns1.5ns1.5ns0.2ns

0.20.4

nsns

See Figure11

See Figure10See Figure12

Parameter Measurement Information: VDD at 3.3V to 2.5V

Figure 3. Load Circuit [3,4,5]

Figure 5. Point to Point Load Circuit[3,4,5]

From OutputUnder TestCL = 50 pF500 ohmFrom OutputUnder TestCL = 3 pF500 ohmFigure 4. Voltage Waveforms Propagation Delay Times[6]

0.8VDDFigure 6. Voltage Waveforms – Pulse Duration[4]

tw(50-50)InputVDD/2VDD/20 Vtw(20-80)0.8VDDInputtPLHOutputVDD/2VDD/20 VtPHLVDD/2VDD/2VOHVOL0.8VDDVDD/20 VInputDocument #: 38-07348 Rev. *CPage 6 of 11

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CY2CC910

Parameter Measurement Information: VDD at 8V

Figure 7. Load Circuit [3,4,5]

Figure 9. Voltage Waveforms – Pulse Duration[4]

tw(50-50)Input0.9V0.9V0 Vtw(20-80)Input0.9V0 V1.8VFrom OutputUnder TestCL = 6 pF500 ohm1.8VFigure 8. Voltage Waveforms Propagation

1.8VFigure 10. Pulse Skew - tsk(p)

3VInputtPLHOutput0.9V0.9V1.5V0 VtPHLINPUTtPLHtPHL0VVOH1.5VVOL0.9V0.9VVOHVOLOUTPUTtsk(P) = l tPHL - tPLH lFigure 11. Output Skew - tsk(0)

3V1.5VINPUTtPLH1tPHL10VVOH1.5VOUTPUT 1tsk(O)tsk(O)VOLVOH1.5VVOLOUTPUT 2tPLH 2tPLH 2tsk(P) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 lNotes

3.CL includes probe and jig capacitance.

4.All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50Ω, tR < 2.5 ns, tF < 2.5 ns.5.The outputs are measured one at a time with one transition per measurement.6.TPLH and TPHL are the same as tpd.

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CY2CC910

Figure 12. Package Skew - tsk(t)

3V1.5VINPUTtPLH1tPHL10VVOH1.5VPACKAGE 1 OUTPUTtsk(t)tsk(t)VOLVOH1.5VVOL PACKAGE 2 OUTPUTtPLH 2tPLH 2tsk(t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 lOrdering Information

Part NumberCY2CC910SICY2CC910SITCY2CC910SCCY2CC910SCTCY2CC910OICY2CC910OITCY2CC910OCCY2CC910OCTPb-freeCY2CC910OXICY2CC910OXITCY2CC910OXCCY2CC910OXCTPackage Type20-pin SOIC20-pin SOIC–Tape and Reel20-pin SOIC20-pin SOIC–Tape and Reel20-pin SSOP20-pin SSOP–Tape and Reel20-pin SSOP20-pin SSOP–Tape and ReelProduct FlowIndustrial, –40° to 85°CIndustrial, –40° to 85°CCommercial, 0°C to 70°CCommercial, 0°C to 70°CIndustrial, –40° to 85°CIndustrial, –40° to 85°CCommercial, 0°C to 70°CCommercial, 0°C to 70°CStatusObsoleteObsoleteObsoleteObsoleteObsoleteObsoleteObsoleteObsolete20-pin SSOP20-pin SSOP–Tape and Reel20-pin SSOP20-pin SSOP–Tape and ReelIndustrial, –40° to 85°CIndustrial, –40° to 85°CCommercial, 0°C to 70°CCommercial, 0°C to 70°CActiveActiveActiveActiveDocument #: 38-07348 Rev. *CPage 8 of 11

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Package Drawing and Dimensions

Figure 13. 20-Pin (300-Mil) SOIC S5 (51-85024)

51-85024 *C

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Figure 14. 20-Pin Shrunk Small Outline Package O20

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CY2CC910

Document History Page

Document Title: CY2CC910 1:10 Clock Fanout BufferDocument No: 38-07348Rev.

ECN NO.

Orig. of Change

Submission

Date

Description of Change

***A

114318119148

TSMRGL

05/10/0210/07/02

New Data Sheet

Added 5.8 as the Max. value for VIH in the DC Electrical Characteristics @3.3V table.

Changed the Max. value of VIH from 5.8 to 5.0 in the DC Electrical Charac-teristics @2.5V table.

Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical Characteristics @1.8V table.Added Lead-free devices for SSOP

Added “Status” column to Ordering Information tableUpdated Package Diagram 51-85024Updated template

*B*C

4042872595534

RGLCXQ/PYRS

See ECN10/23/08

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© Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use ofany circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used formedical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use ascritical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systemsapplication implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypressintegrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited withoutthe express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does notassume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems wherea malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturerassumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-07348 Rev. *CRevised October 22, 2008Page 11 of 11

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