ARM7 3 stages pipeline -- F D E M W (it also has 5 steps run a instruction, but as its architecture is Von Neumann, with only 1 internal bus for data and instruction,
So the memory access and write back data operator will be blocked with fetch instruction operator, So we call ARM7 as 3 stages pipeline.)
ARM9 5 stages pipeline --- F D E M W --- depending on its Harvard architecture. (2 separate bus -- data bus and instruction bus, separate cache----D Cache I Cache,
MMU(ARM9TDMI), write buffer(can consider it as write cache))
MMU---- 1. memory protection unit, 2. virtual address transfer to physical address
cache and write buffer,
the component on board have different speed, such as CPU always has 1GHZ or more, Memory has 100MHZ（just for example）,
the memory will block the cpu clock cycle when cpu do the memory access or fetch instruction directly from memory.
So the i, d cache and write buffer appears. Sometimes cache has such as 300MHZ which is close the register's speed.
About the pipeline and exception
When exception and function call happens, it will break the arm pipeline.
For example, we use b or bl for branch to a label or a child function,
F D E M W
F D E L A ------ bl func ----PC - 8
F D ----------- PC-4
F ---------PC
F D E M W
when we execute the b or bl instruction, the pc is currently in +8 offset position. So the bl address should be PC-8, and the branch instruction will break the pipeline, return the link ret to lr, and do the adjust lr = lr-4.
So for the function call, when we want to return to the parent function, we just can use MOV PC LR, then it's OK.
similar, the exception also will break the pipeline. For example:
1. irq:
irq
|
PC-12 F D E M W
PC-8 F D E M W
PC-4 F D E M W
PC F D E M W
PC+4 F D E M W
when irq happen, now cpu instruction execute is PC-8, it will execute it done. And now PC will be save to lr.(always exception will do that, branch with link register will adjust the lr , so the lr=pc-4). Therefore, when we need return from irq_handle, we should adjust lr mannully, such as subs pc, lr, #4.
2. data abort
abt
|
PC-12 F D E M W
PC-8 F D E M W
PC-4 F D E M W
PC F D E M W
PC+4 F D E M W
data abort happened in Memory Access stage, so the instruction abort happens in PC-12 address. So when we need to return from data abort handle, we should subs pc, lr, #8 for continue PC.
3. SWI
SWI
|
PC-8 F D E M W
PC-4 F D E M W
PC F D E M W
PC+4 F D E M W
PC+8 F D E M W
the SWI exception happens in decode stage, PC will store to lr, and just use LR as return address is OK.
4. pre-fetch abort
pre-fetch
|
PC-8 F D E M W
PC-4 F D E M W
PC F D E M W
PC+4 F D E M W
PC+8 F D E M W
指令预取中止异常中断由当前执行的指令在ALU里执行时产生，当指令预取中止异常中断发生时，程序计数器pc的值还未更新，它指向当前指令后面第2条指令（对于ARM指令，它指向当前指令地址加8字节的位置；对于Thumb指令，它指向当前指令地址加4字节的位置）。此时处理器将值（pc-4）保存到lr_abt中，它指向当前指令的下一条指令，所以返回操作可以通过下面指令实现：SUBS PC，LR_abt，#4
2012.09.11
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