专利名称：Method, system, and apparatus for
incremental design in programmable logicdevices using floorplanning
发明人：Rajat Aggarwal,Guenter Stenz,Srinivasan
Dasasathyan
申请号：US10812550申请日：20040329公开号：US07149993B1公开日：20061212
专利附图：
摘要：A method of designing a programmable logic device can include receiving a
modification to a programmable logic device that has been floorplanned. Modules of theprogrammable logic device that have been changed by the modification can be identified.The changed modules can be floorplanned thereby determining a placement solutionthat does not violate boundaries of unchanged modules. The programmable logic devicethen can be placed and routed.
申请人：Rajat Aggarwal,Guenter Stenz,Srinivasan Dasasathyan
地址：Sunnyvale CA US,Campbell CA US,Sunnyvale CA US
国籍：US,US,US
代理人：Pablo Meles,Kim Kanzaki,Kevin Cuenot
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