元器件交易网www.cecb2b.comMC14015BDual4-BitStaticShiftRegisterThe MC14015B dual 4–bit static shift register is constructed withMOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. It consists of two identical, independent4–state serial–input/parallel–output registers. Each register hasindependent Clock and Reset inputs with a single serial Data input.The register states are type D master–slave flip–flops. Data is shiftedfrom one stage to the next during the positive–going clock transition.Each register can be cleared when a high level is applied on the Resetline. These complementary MOS shift registers find primary use inbuffer storage and serial–to–parallel conversion where low powerdissipation and/or noise immunity is desired.http://onsemi.comMARKINGDIAGRAMS16PDIP–16P SUFFIXCASE 648MC14015BCPAWLYYWW116SOIC–16D SUFFIXCASE 751B116TSSOP–16DT SUFFIXCASE 948F114015BALYW14015BAWLYWW•Diode Protection on All Inputs•Supply Voltage Range = 3.0 Vdc to 18 Vdc•Logic Edge–Clocked Flip–Flop Design —Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive goingedge of the clock pulse.Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range.•MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)SymbolVDDVin, VoutIin, IoutPDTATstgTLParameterDC Supply Voltage RangeInput or Output Voltage Range(DC or Transient)Input or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)Ambient Temperature RangeStorage Temperature RangeLead Temperature(8–Second Soldering)Value–0.5 to +18.0–0.5 to VDD + 0.5±10500–55 to +125–65 to +150260UnitVVmAmW°C°C°CSOEIAJ–16F SUFFIXCASE 96616MC14015BAWLYWW1A= Assembly LocationWL or L= Wafer LotYY or Y= YearWW or W= Work WeekORDERING INFORMATIONDeviceMC14015BCPMC14015BDMC14015BDR2MC14015BDTMC14015BFMC14015BFELPackagePDIP–16SOIC–16SOIC–16Shipping2000/Box48/Rail2500/Tape & Reel2.Maximum Ratings are those values beyond which damage to the devicemay occur.3.Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, Vin and Vout should be constrainedto the range VSS v (Vin or Vout) v VDD.Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either VSS or VDD). Unused outputs must be left open.TSSOP–162000/Tape & ReelSOEIAJ–16SOEIAJ–16See Note 1.See Note 1.1.For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 20001March, 2000 – Rev. 3Publication Order Number:MC14015B/D元器件交易网www.cecb2b.comMC14015BTRUTH TABLECD01XXXR0001Q001No Change0QnQn–1Qn–1No Change0X = Don’t CareQn = Q0, Q1, Q2, or Q3, as applicable.Qn–1 = Output of prior stage.PIN ASSIGNMENTCBQ3BQ2AQ1AQ0ARADAVSS12345678161514131211109VDDDBRBQ0BQ1BQ2BQ3ACABLOCK DIAGRAMQ07DQ1Q296Q015DQ1Q2114VDD = PIN 16VSS = PIN 8CRQ31312112CRQ354310http://onsemi.com2元器件交易网www.cecb2b.comMC14015BELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)CharacteristicSymbolVOLVDDVdc5.010155.010155.010155.010155.05.010155.0101515—5.010155.01015– 55_CMin———25_C125_CMaxMin———Typ (4.)000MaxMin———MaxUnitVdcOutput VoltageVin = VDD or 0Vin = 0 or VDD“0” Level0.050.050.05———0.050.050.05———0.050.050.05———“1” LevelVOH4.959.9514.95———4.959.9514.95———5.010154.959.9514.95———VdcInput Voltage“0” Level(VO = 4.5 or .05 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)VIL1.53.04.0——————————2.254.506.752.755.508.251.53.04.0——————————1.53.04.0——————————Vdc(VO = 0.5 or 4.5 Vdc)“1” Level(VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)VIH3.57.0113.57.0113.57.011VdcOutput Drive Current(VOH = 2.5 Vdc) (VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)(VOL = 0.4 Vdc) (VOL = 0.5 Vdc)(VOL = 1.5 Vdc)SourceIOHmAdc– 3.0– 0.64– 1.6– 4.20.641.64.2—————– 2.4– 0.51– 1.3– 3.40.511.33.4—————– 4.2– 0.88– 2.25– 8.80.882.258.8– 1.7– 0.36– 0.9– 2.40.360.92.4—————SinkIOLmAdcInput CurrentInput Capacitance(Vin = 0)IinCinIDD± 0.1—5.01020±0.000015.00.0050.0100.015± 0.17.55.01020± 1.0—150300600µAdcpFµAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package) (CL = 50 pF on all outputs, all buffers switching)ITIT = (1.2 µA/kHz)f + IDDIT = (2.4 µA/kHz)f + IDDIT = (3.6 µA/kHz)f + IDDµAdc4.Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5.The formulas given are for the typical characteristics only at 25_C.6.To calculate total supply current at loads other than 50 pF:IT(CL) = IT(50 pF) + (CL – 50) Vfkwhere: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.http://onsemi.com3元器件交易网www.cecb2b.comMC14015BSWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)CharacteristicOutput Rise and Fall TimetTLH, tTHL = (1.5 ns/pF) CL + 25 nstTLH, tTHL = (0.75 ns/pF) CL + 12.5 nstTLH, tTHL = (0.55 ns/pF) CL + 9.5 nsSymboltTLH,tTHLVDD5.01015Min———Typ (8.)1005040Max20010080UnitnsPropagation Delay TimeClock, Data to QtPLH, tPHL = (1.7 ns/pF) CL + 225 nstPLH, tPHL = (0.66 ns/pF) CL + 92 nstPLH, tPHL = (0.5 ns/pF) CL + 65 nsReset to QtPLH, tPHL = (1.7 ns/pF) CL + 375 nstPLH, tPHL = (0.66 ns/pF) CL + 147 nstPLH, tPHL = (0.5 ns/pF) CL + 95 nsClock Pulse WidthtPLH,tPHLns5.010155.010155.010155.010155.010155.010155.01015——————3101259046018012018585552.06.07.5———750250170750250170———tWH400175135——————nsClock Pulse Frequencyfcl1.53.03.751554——————MHzClock Pulse Rise and Fall TimestTLH, tTHLµsReset Pulse WidthtWH4001601203501007520080601005040nsSetup Timetsuns7.The formulas given are for typical characteristics only at 25_C.8.Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.VDDPULSEGENERATOR2PULSEGENERATOR1500 µFDCRIDVDDQ0Q1Q2Q3CLVSS1fCLOCK50%0.01 µFCERAMICCLCLCLDATAFigure 1. Power Dissipation Test Circuit and Waveformhttp://onsemi.com4元器件交易网www.cecb2b.comMC14015BtTLHDATAINPUTtsuPULSEGENERATOR2SYNCPULSEGENERATOR1CRVDDDQ0Q1Q2Q3CLVSStWL = tWH = 50% Duty CycletTLH = tTHL ≤ 20 nsQ0tTLHCLCLCLtTLHCLOCKINPUTtWHtPLHt–tTHL90%50%10%tTHL90%50%10%tWLtPHL90%50%10%tTHLVDD0 VVDD0 VFigure 2. Switching Test Circuit and WaveformsPULSEGENERATOR2SYNCPULSEGENERATOR1VDDDQ0Q1Q2CRQ3CLVSSCLDATAINPUT50%CLCLCLOCKINPUT50%tsuthVDD0 VVDD0 VFigure 3. Setup and Hold Time Test Circuit and Waveformshttp://onsemi.com5SINGLE BITVDDQ元器件交易网www.cecb2b.comRESETCLOCKDATAINTO D OFNEXT BITVSSMC14015BCIRCUIT SCHEMATICShttp://onsemi.comRESET INPUT BUFFERVDDVDDDATA TOFIRST BITRESETINVSSVSS6DATA INPUT BUFFERCLOCK INPUT BUFFERVDDDATAINRESETTO 4 BITSCLOCKINCLOCKTO 4 BITSVSS元器件交易网www.cecb2b.comMC14015BLOGIC DIAGRAMSSINGLE BITCDATACCCCCQTO D OFNEXT BITCRESETCCCCCOMPLETE DEVICE5DATA INPUT BUFFER7DDCLOCK INPUT BUFFERCRQQDCRQQDCRQQDCRQQQ04Q13Q210Q396CRRESET INPUT BUFFERD15CLOCK INPUT BUFFERDATA INPUT BUFFERDCRQQ13Q012Q111Q22Q3DCRQQDCRQQDCRQQ114CRVDD = PIN 16VSS = PIN 8RESET INPUT BUFFERhttp://onsemi.com7元器件交易网www.cecb2b.comMC14015BPACKAGE DIMENSIONS–A–169PDIP–16P SUFFIXPLASTIC DIP PACKAGECASE 648–08ISSUE RB18NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.DIMABCDFGHJKLMSINCHESMILLIMETERSMINMAXMINMAX0.7400.77018.8019.550.2500.2706.356.850.1450.1753.694.440.0150.0210.390.530.0400.701.021.770.100 BSC2.54 BSC0.050 BSC1.27 BSC0.0080.0150.210.380.1100.1302.803.300.2950.3057.507.740 10 0 10 ____0.0200.0400.511.01FSCL–T–HKGD16 PLSEATINGPLANEJTAMM0.25 (0.010)Mhttp://onsemi.com8元器件交易网www.cecb2b.comMC14015BPACKAGE DIMENSIONSSOIC–16D SUFFIXPLASTIC SOIC PACKAGECASE 751B–05ISSUE JNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERSINCHESMINMAXMINMAX9.8010.000.3860.3933.804.000.1500.1571.351.750.0540.0680.350.490.0140.0190.401.250.0160.0491.27 BSC0.050 BSC0.190.250.0080.0090.100.250.0040.0090 7 0 7 ____5.806.200.2290.2440.250.500.0100.019–A–169–B–18P8 PL0.25 (0.010)MBSGFKC–T–SEATINGPLANERX 45_MD16 PLMJ0.25 (0.010)TBSASDIMABCDFGJKMPRhttp://onsemi.com9元器件交易网www.cecb2b.comMC14015BPACKAGE DIMENSIONSTSSOP–16DT SUFFIXPLASTIC TSSOP PACKAGECASE 948F–01ISSUE O16X REFK0.10 (0.004)0.15 (0.006)TUSMTUSVSKK1169NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLDFLASH. PROTRUSIONS OR GATE BURRS. MOLDFLASH OR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.7.DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE –W–.DIMABCDFGHJJ1KK1LMMILLIMETERSMINMAX4.905.104.304.50–––1.200.050.150.500.750.65 BSC0.180.280.090.200.090.160.190.300.190.256.40 BSC0 8 __INCHESMINMAX0.1930.2000.1690.177–––0.0470.0020.0060.0200.0300.026 BSC0.0070.0110.0040.0080.0040.0060.0070.0120.0070.0100.252 BSC0 8 __2XL/2J1B–U–LPIN 1IDENT.18SECTION N–NJN0.15 (0.006)TUS0.25 (0.010)MA–V–NFDETAIL EC0.10 (0.004)–T–SEATINGPLANE–W–DGHDETAIL Ehttp://onsemi.com10元器件交易网www.cecb2b.comMC14015BPACKAGE DIMENSIONSSOEIAJ–16F SUFFIXPLASTIC EIAJ SOIC PACKAGECASE 966–01ISSUE O169LEQ1EHEM_LDETAIL P18ZDeAVIEW PNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.5.THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).DIMAA1bcDEeHELLEMQ1ZMILLIMETERSMINMAX–––2.050.050.200.350.500.180.279.9010.505.105.451.27 BSC7.408.200.500.851.101.500 _10 _0.700.90–––0.78INCHESMINMAX–––0.0810.0020.0080.0140.0200.0070.0110.3900.4130.2010.2150.050 BSC0.2910.3230.0200.0330.0430.0590 _10 _0.0280.035–––0.031cb0.13 (0.005)MA10.10 (0.004)http://onsemi.com11元器件交易网www.cecb2b.com
MC14015B
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