元器件交易网www.cecb2b.comMOTOROLASEMICONDUCTOR TECHNICAL DATAOrder this documentby MCM69P618C/D64K x 18 Bit Pipelined BurstRAMSynchronous Fast Static RAMThe MCM69P618C is a 1M–bit synchronous fast static RAM designed to pro-vide a burstable, high performance, secondary cache for the 68K Family,PowerPC™, 486, i960™, and Pentium™ microprocessors. It is organized as 64Kwords of 18 bits each. This device integrates input registers, an output register,a 2–bit address counter, and high speed SRAM onto a single monolithic circuitfor reduced parts count in cache data RAM applications. Synchronous designallows precise cycle control with the use of an external clock (K). BiCMOS cir-cuitry reduces the overall power consumption of the integrated functions forgreater reliability.Addresses (SA), data inputs (DQx), and all control signals except outputenable (G) and Linear Burst Order (LBO) are clock (K) controlled throughpositive–edge–triggered noninverting registers.Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burstaddresses can be generated internally by the MCM69P618C (burst sequenceoperates in linear or interleaved mode dependent upon the state of LBO) andcontrolled by the burst address advance (ADV) input pin.Write cycles are internally self–timed and initiated by the rising edge of theclock (K) input. This feature eliminates complex off–chip write pulse generationand provides increased timing flexibility for incoming signals.Synchronous byte write (SBx), synchronous global write (SGW), and syn-chronous write enable SW are provided to allow writes to either individual bytesor to both bytes. The two bytes are designated as “a” and “b”. SBa controls DQaand SBb controls DQb. Individual bytes are written if the selected byte writes SBxare asserted with SW. Both bytes are written if either SGW is asserted or if bothSBx and SW are asserted.For read cycles, pipelined SRAMs output data is temporarily stored by anedge–triggered output register and then released to the output buffers at the nextrising edge of clock (K).The MCM69P618C operates from a single 3.3 V power supply and all inputsand outputs are LVTTL compatible and 5 V tolerant.•MCM69P618C–4 = 4 ns Access / 7.5 ns CycleMCM69P618C–4.5 = 4.5 ns Access / 8 ns CycleMCM69P618C–5 = 5 ns Access / 10 ns CycleMCM69P618C–6 = 6 ns Access / 12 ns CycleMCM69P618C–7 = 7 ns Access / 13.3 ns Cycle•Single 3.3 V + 10%, – 5% Power Supply•ADSP, ADSC, and ADV Burst Control Pins•Selectable Burst Sequencing Order (Linear/Interleaved)•Internally Self–Timed Write Cycle•Byte Write and Global Write Control•Single–Cycle Deselect Timing•5 V Tolerant on all Pins (Inputs and I/Os)•100–Pin TQFP PackageMCM69P618CTQ PACKAGETQFPCASE 983A–01The PowerPC name is a trademark of IBM Corp., used under license therefrom.i960 and Pentium are trademarks of Intel Corp.REV 22/16/98© Motorola, Inc. 1998MOTOROLA FAST SRAMMCM69P618C1元器件交易网www.cecb2b.comFUNCTIONAL BLOCK DIAGRAMLBOADVKADSCADSPK2BURSTCOUNTERCLR221664K x 18 ARRAYSASA1SA0ADDRESSREGISTER1614SGWSWWRITEREGISTERa2WRITEREGISTERbDATA–INREGISTERKDATA–0UTREGISTER1818SBaSBbK2KSE1SE2SE3GENABLEREGISTERENABLEREGISTERDQa, DQbMCM69P618C2MOTOROLA FAST SRAM元器件交易网www.cecb2b.comPIN ASSIGNMENTSASASE1SE2NCNCSBbSBaSE3VDDVSSKSGWSWGADSCADSPADVSASANCNCNCVDDVSSNCNCDQbDQbVSSVDDDQbDQbNCVDDNCVSSDQbDQbVDDVSSDQbDQbDQbNCVSSVDDNCNCNC100999897969594939291908988878685848382811802793784775766757748739721071117012691368146715661665176418631962206121602259235824572556552627542853295230513132333435363738394041424344454647484950LBOSASASASASA1SA0NCNCVSSVDDNCNCSASASASASANCNCSANCNCVDDVSSNCDQaDQaDQaVSSVDDDQaDQaVSSNCVDDNCDQaDQaVDDVSSDQaDQaNCNCVSSVDDNCNCNCMOTOROLA FAST SRAMMCM69P618C3元器件交易网www.cecb2b.comPIN DESCRIPTIONSPin Locations8584SymbolADSCADSPTypeInputInputDescriptionSynchronous Address Status Controller: Initiates READ, WRITE, orchip deselect cycle.Synchronous Address Status Processor: Initiates READ, WRITE, orchip deselect cycle (exception — chip deselect does not occur whenADSP is asserted and SE1 is high).Synchronous Address Advance: Increments address count inaccordance with counter type selected (linear/interleaved).Synchronous Data I/O: “x” refers to the byte being read or written(byte a, b).Asynchronous Output Enable Input:Low — enables output buffers (DQx pins).High — DQx pins are high impedance.Clock: This signal registers the address, data in, and all control signalsexcept G and LBO.Linear Burst Order Input: This pin must remain in steady state (thissignal not registered or latched). It must be tied high or low.Low — linear burst counter (68K/PowerPC).High — interleaved burst counter (486/i960/Pentium).Synchronous Address Inputs: These inputs are registered and mustmeet setup and hold times.Synchronous Address Inputs: These pins must be wired to the twoLSBs of the address bus for proper burst operation. These inputs areregistered and must meet setup and hold times.Synchronous Byte Write Inputs: “x” refers to the byte being written (bytea, b). SGW overrides SBx.Synchronous Chip Enable: Active low to enable chip.Negated high–blocks ADSP or deselects chip when ADSC is asserted.Synchronous Chip Enable: Active high for depth expansion.Synchronous Chip Enable: Active low for depth expansion.Synchronous Global Write: This signal writes all bytes regardless of thestatus of the SBx and SW signals. If only byte write signals SBx arebeing used, tie this pin high.Synchronous Write: This signal writes only those bytes that have beenselected using the byte write SBx pins. If only byte write signals SBxare being used, tie this pin low.Power Supply: 3.3 V + 10%, –5%.Ground.No Connection: There is no connection to the chip. For compatibilityreasons, it is recommended that this pin be tied low for system designsthat do not have a sleep mode associated with the cache/memorycontroller. Other vendors’ RAMs may have implemented the SleepMode (ZZ) feature.No Connection: There is no connection to the chip.83(a) 58, 59, 62, 63, 68, 69, 72, 73, 74(b) 8, 9, 12, 13, 18, 19, 22, 23, 2486ADVDQxGInputI/OInput8931KLBOInputInput32, 33, 34, 35, 44, 45, 46, 47, 48, 80, 81, 82, 99, 10036, 37SASA1,SA0InputInput93, 94(a) (b)98979288SBxSE1SE2SE3SGWInputInputInputInputInput87SWInput4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 915, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 9064VDDVSSNCSupplySupplyInput1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 43, 49, 50, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96NC—MCM69P618C4MOTOROLA FAST SRAM元器件交易网www.cecb2b.comTRUTH TABLE (See Notes 1 through 4)Next CycleDeselectDeselectDeselectDeselectDeselectBegin ReadBegin ReadContinue ReadContinue ReadContinue ReadContinue ReadSuspend ReadSuspend ReadSuspend ReadSuspend ReadBegin WriteBegin WriteBegin WriteContinue WriteContinue WriteSuspend WriteSuspend WriteAddressUsedNoneNoneNoneNoneNoneExternalExternalNextNextNextNextCurrentCurrentCurrentCurrentCurrentCurrentExternalNextNextCurrentCurrentSE1100XX00XX11XX11X10X1X1SE2XX0X011XXXXXXXXXX1XXXXSE3X1X1X00XXXXXXXXXX0XXXXADSPX00110111XX11XX1X11X1XADSC0XX00X0111111111101111ADVXXXXXXX0000111111X0011G 3XXXXXXX10101010XXXXXXXDQxHigh–ZHigh–ZHigh–ZHigh–ZHigh–ZHigh–ZHigh–ZHigh–ZDQHigh–ZDQHigh–ZDQHigh–ZDQHigh–ZHigh–ZHigh–ZHigh–ZHigh–ZHigh–ZHigh–ZWrite 2, 4XXXXXREADREADREADREADREADREADREADREADREADREADWRITEWRITEWRITEWRITEWRITEWRITEWRITENOTES:1.X = Don’t Care. 1 = logic high. 0 = logic low.2.Write is defined as either 1) any SBx and SW low or 2) SGW is low.3.G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.4.On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. Gmust also remain negated at the completion of the write cycle to ensure proper write data hold times.LINEAR BURST ADDRESS TABLE (LBO = VSS)1st Address (External)X . . . X00X . . . X01X . . . X10X . . . X112nd Address (Internal)X . . . X01X . . . X10X . . . X11X . . . X003rd Address (Internal)X . . . X10X . . . X11X . . . X00X . . . X014th Address (Internal)X . . . X11X . . . X00X . . . X01X . . . X10INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)1st Address (External)X . . . X00X . . . X01X . . . X10X . . . X112nd Address (Internal)X . . . X01X . . . X00X . . . X11X . . . X103rd Address (Internal)X . . . X10X . . . X11X . . . X00X . . . X014th Address (Internal)X . . . X11X . . . X10X . . . X01X . . . X00WRITE TRUTH TABLECycle TypeReadReadWrite Byte aWrite Byte bWrite All BytesWrite All BytesSGWHHHHHLSWHLLLLXSBaXHLHLXSBbXHHLLXMOTOROLA FAST SRAMMCM69P618C5元器件交易网www.cecb2b.comABSOLUTE MAXIMUM RATINGS (See Note 1)RatingPower Supply VoltageVoltage Relative to VSS for AnyPin Except VDDOutput Current (per I/O)Package Power Dissipation (See Note 2)Temperature Under BiasStorage TemperatureSymbolVDDVin, VoutIoutPDTbiasTstgValue– 0.5 to + 4.6– 0.5 to 6.0± 201.6– 10 to 85– 55 to 125UnitVVmAW°C°CThis device contains circuitry to protect theinputs against damage due to high static volt-ages or electric fields; however, it is advisedthat normal precautions be taken to avoidapplication of any voltage higher than maxi-mum rated voltages to this high–impedancecircuit.NOTES:1.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS areexceeded. Functional operation should be restricted to RECOMMENDED OPER–ATING CONDITIONS. Exposure to higher than recommended voltages for extendedperiods of time could affect device reliability.2.Power dissipation capability is dependent upon package characteristics and useenvironment. See Package Thermal Characteristics.PACKAGE THERMAL CHARACTERISTICSRatingThermal Resistance Junction to Ambient (@ 200 lfm)Thermal Resistance Junction to Board (Bottom)Thermal Resistance Junction to Case (Top)Single–Layer BoardFour–Layer BoardSymbolRθJARθJBRθJCMax4025179Unit°C/W°C/W°C/WNotes1, 21, 31, 4NOTES:1.Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambienttemperature, air flow, board population, and board thermal resistance.2.Per SEMI G38–87.3.Indicates the average thermal resistance between the die and the printed circuit board.4.Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method1012.1).MCM69P618C6MOTOROLA FAST SRAM元器件交易网www.cecb2b.comDC OPERATING CONDITIONS AND CHARACTERISTICS(VDD = 3.3 V + 10%, –5%, TA = 0 to 70°C, Unless Otherwise Noted)RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)ParameterSupply VoltageInput Low VoltageInput High Voltage*VIL ≥– 2 V for t ≤tKHKH/2.**VIH ≤ 6 V for t ≤ tKHKH/2.SymbolVDDVILVIHMin3.135– 0.5*2Typ3.3——Max3.60.85.5**UnitVVVDC CHARACTERISTICS AND SUPPLY CURRENTSParameterInput Leakage Current (0 V ≤ Vin ≤ VDD) (Excluding LBO)Output Leakage Current (0 V ≤ Vin ≤ VDD)AC Supply Current (Device Selected, All Outputs Open,Cycle Time ≥ tKHKH min)MCM69P618C–4MCM69P618C–4.5MCM69P618C–5MCM69P618C–6MCM69P618C–7MCM69P618C–4MCM69P618C–4.5MCM69P618C–5MCM69P618C–6MCM69P618C–7MCM69P618C–4MCM69P618C–4.5MCM69P618C–5MCM69P618C–6MCM69P618C–7SymbolIlkg(I)Ilkg(O)IDDAMin———Max± 1± 130029527526025516015513011010550504540400.4—UnitµAµAmA1, 2, 3NotesCMOS Standby Supply Current (Deselected, Clock (K)Cycle Time ≥ tKHKH, All Inputs Toggling at CMOSLevels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)ISB1—mA4Clock Running Supply Current (Deselected, Clock (K)Cycle Time ≥ tKHKH, All Other Inputs Held to StaticCMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)ISB2—mA4Output Low Voltage (IOL = 8 mA)Output High Voltage (IOH = – 4 mA)NOTES:1.Reference AC Operating Conditions and Characteristics for input and timing.2.All addresses transition simultaneously low (LSB) and then high (MSB).3.Data states are all zero.4.Device in Deselected mode as defined by the Truth Table.VOLVOH—2.4VVCAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)ParameterInput CapacitanceInput/Output CapacitanceSymbolCinCI/OMin——Typ47Max69UnitpFpFMOTOROLA FAST SRAMMCM69P618C7元器件交易网www.cecb2b.comAC OPERATING CONDITIONS AND CHARACTERISTICS(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)Input Timing Measurement Reference Level. . . . . . . . . . . . . . . 1.5 VInput Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 VInput Rise/Fall Time. . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)Output Timing Reference Level. . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 VOutput Load. . . . . . . . . . . . . . See Figure 1 Unless Otherwise NotedREAD/WRITE CYCLE TIMING (See Notes 1, 2, and 3)69P618C–4PParameterCycle TimeClock High Pulse WidthClock Low Pulse WidthClock Access TimeOutput Enable to Output ValidClock High to Output ActiveClock High to Output ChangeOutput Enable to OutputActiveOutput Disable to Q High–ZClock High to Q High–ZSetup Times:AddressADSP, ADSC, ADVData InWriteChip EnableHold Times: AddressADSP, ADSC, ADVData InWriteChip EnableSblSymboltKHKHtKHKLtKLKHtKHQVtGLQVtKHQX1tKHQX2tGLQXtGHQZtKHQZtADKHtADSKHtDVKHtWVKHtEVKHtKHAXtKHADSXtKHDXtKHWXtKHEXMin7.533——1.51.50—22Max———44———44—69P618C–4.5Min833——1.51.50—22.5Max———4.54.5———4.54.5—69P618C–5Min1033——020—22.5Max———55———55—69P618C–6Min1244——020—22.5Max———65———55—69P618C–7Min13.34.54.5——020—22.5Max———76———55—UiUnitnsnsnsnsnsnsnsnsnsnsns4444, 54, 5NNotes0.5—0.5—0.5—0.5—0.5—nsNOTES:1.Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high and SE3 low whenever ADSPor ADSC is asserted.2.All read and write cycle timings are referenced from K or G.3.G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.4.This parameter is sampled and not 100% tested.5.Measured at ± 200 mV from steady state.OUTPUTZ0 = 50 ΩRL = 50 ΩVT = 1.5 VFigure 1. AC Test LoadMCM69P618C8MOTOROLA FAST SRAMREAD/WRITE CYCLEStKHKLtKLKHtKHKHK元器件交易网www.cecb2b.comMOTOROLA FAST SRAMBCDtKHQVBURST WRAPS AROUNDQ(A)tKHQX2Q(B)Q(B+1)Q(B+2)Q(B+3)tGHQZQ(B)D(C)ADSP, SASE2, SE3IGNOREDBURST READBURST WRITED(C+1)D(C+2)D(C+3)tGLQXQ(D)SINGLE READSAAADSPADSCADVSE1EWGtKHQVDQxQ(n)tKHQZtKHQX1DESELECTEDSINGLE READMCM69P618C9NOTE: E low = SE2 high and SE3 low.W low = SGW low and/or SW and SBx low.元器件交易网www.cecb2b.comAPPLICATION INFORMATIONThe MCM69P618C BurstRAM is a high speed synchro-nous SRAM that is intended for use primarily in secondary orlevel two (L2) cache memory applications. L2 caches arefound in a variety of classes of computers — from the desk-top personal computer to the high–end servers and trans-action processing machines. For simplicity, the majority of L2caches today are direct mapped and are single bank imple-mentations. These caches tend to be designed for busspeeds in the range of 33 to 66 MHz. At these bus rates,non–pipelined (flow–through) BurstRAMs can be used sincetheir access times meet the speed requirements for a mini-mum–latency, zero–wait state L2 cache interface. Latency isa measure (time) of “dead” time the memory system exhibitsas a result of a memory request.For those applications that demand bus operation at great-er than 66 MHz or multi–bank L2 caches at 66 MHz, the pipe-lined (register/register) version of the 64K x 18 BurstRAM(MCM69P618C) allows the user to configure the RAM tosupport such designs. Multiple banks of BurstRAMs createadditional bus loading and can cause the system to other-wise miss its timing requirements. The access time (clock–to–valid–data) of a pipelined BurstRAM is inherently fasterthan a non–pipelined device by a few nanoseconds. Thisdoes not come without cost. The cost is latency — “dead”time.Since most L2 caches are tied to the processor bus andbus speeds continue to increase over time, pipelined (R/R)BurstRAMs are the best choice in achieving zero–wait stateL2 cache performance. At bus speeds ranging from 66 MHzto 100 MHz, pipelined BurstRAMs are able to provide fastclock to valid data times required of these high speed buses.NON–BURST SYNCHRONOUS OPERATIONAlthough this BurstRAM has been designed for 68K–,PowerPC–, 486–, i960–, and Pentium–based systems,these SRAMs can be used in other high speed L2 cache ormemory applications that do not require the burst addressfeature. Most L2 caches designed with a synchronous inter-face can make use of the MCM69P618C. The burst counterfeature of the BurstRAM can be disabled, and the SRAM canbe configured to act upon a continuous stream of addresses.See Figure 2.CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL)Non–BurstSync Non–Burst,Pipelined SRAMADSPHADSCLADVHSE1LSE2HLBOXNOTE:Although X is specified in the table as a don’t care, the pinmust be tied either high or low.KADDRABCDEFGHSE3WGDQQ(A)Q(B)Q(C)Q(D)D(E)D(F)D(G)D(H)READSWRITESFigure 2. Example Configuration as Non–Burst Synchronous SRAMMCM69P618C10MOTOROLA FAST SRAM元器件交易网www.cecb2b.comORDERING INFORMATION(Order by Full Part Number)MCMMotorola Memory PrefixPart Number69P618CXXXXBlank = Trays, R = Tape and ReelSpeed (4 = 4 ns, 4.5 = 4.5 ns, 5 = 5 ns,6 = 6 ns, 7 = 7 ns)Package (TQ = TQFP)Full Part Numbers —MCM69P618CTQ4MCM69P618CTQ4.5MCM69P618CTQ5MCM69P618CTQ6MCM69P618CTQ7MCM69P618CTQ4RMCM69P618CTQ4.5RMCM69P618CTQ5RMCM69P618CTQ6RMCM69P618CTQ7RMotorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.MOTOROLA FAST SRAMMCM69P618C11元器件交易网www.cecb2b.comPACKAGE DIMENSIONSTQ PACKAGETQFPCASE 983A–014Xee/20.20 (0.008)HA–BD –D–80812X 30 TIPS0.20 (0.008)CA–BD5150BE/2BVIEW YE1EE1/2BASEMETALPLATING–X–X=A, B, OR D–A––B–b1c10013031c1bD1/2D1D2X 20 TIPSD/20.13 (0.005)MCA–BSDSSECTION B–BNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DATUM PLANE –H– IS LOCATED AT BOTTOM OFLEAD AND IS COINCIDENT WITH THE LEADWHERE THE LEAD EXITS THE PLASTIC BODY ATTHE BOTTOM OF THE PARTING LINE.4.DATUMS –A–, –B– AND –D– TO BE DETERMINEDAT DATUM PLANE –H–.5.DIMENSIONS D AND E TO BE DETERMINED ATSEATING PLANE –C–.6.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLDPROTRUSION. ALLOWABLE PROTRUSION IS 0.25(0.010) PER SIDE. DIMENSIONS D1 AND B1 DOINCLUDE MOLD MISMATCH AND AREDETERMINED AT DATUM PLANE –H–.7.DIMENSION b DOES NOT INCLUDE DAMBARPROTRUSION. DAMBAR PROTRUSION SHALLNOT CAUSE THE b DIMENSION TO EXCEED 0.45(0.018).DIMAA1A2bb1cc1DD1EE1eLL1L2SR1R2qq 1q 2q 3MILLIMETERSINCHESMINMAXMINMAX–––1.60–––0.0630.050.150.0020.0061.351.450.0530.0570.220.380.0090.0150.220.330.0090.0130.090.200.0040.0080.090.160.0040.00622.00 BSC0.866 BSC20.00 BSC0.787 BSC16.00 BSC0.630 BSC14.00 BSC0.551 BSC0.65 BSC0.026 BSC0.450.750.0180.0301.00 REF0.039 REF0.50 REF0.020 REF0.20–––0.008–––0.08–––0.003–––0.080.200.0030.0080 7 0 7 ____0 –––0 –––__11 _13 _11 _13 _11 _13 _11 _13 _0.20 (0.008)CA–BDA–H––C–SEATINGPLANEq20.10 (0.004)Cq3VIEW AB0.05 (0.002)SSq10.25 (0.010)A2R2GAGE PLANEA1R1L2LL1VIEW ABqHow to reach us:USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;P.O. Box 5405, Denver, Colorado, 80217.1-303-675-2140 or 1-800-441-2447Mfax is a trademark of Motorola, Inc.JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan.03-5487-8488Mfax™: RMFAX0@email.sps.mot.com– TOUCHTONE 1-602-244-6609ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System– US & Canada ONLY 1-800-774-184851 Ting Kok Road, Tai Po, N.T., Hong Kong.852-26629298– http://sps.motorola.com/mfax/HOME PAGE: http://motorola.com/sps/CUSTOMER FOCUS CENTER: 1-800-521-6274MCM69P618C12◊MCM69P618C/DMOTOROLA FAST SRAM