Method for forming interconnect structures

专利名称：Method for forming interconnect structures发明人：Neng-Kuo Chen,Kuo-Hwa Tzeng,Cheng-Yuan

Tsai

申请号：US12179991申请日：20080725公开号：US09245792B2公开日：20160126

专利附图：

摘要：Methods of fabricating interconnect structures in a semiconductor integratedcircuit (IC) are presented. A preferred embodiment comprises forming interconnect linesand vias through a dual-damascenes process. It includes forming a via dielectric layer, an

etch stop layer directly over the via dielectric layer, and a trench dielectric layer over theetch stop layer. The etch stop layer is patterned through a first photolithography andetch process to form openings in the etch stop layer, prior to the formation of the trenchdielectric layer. A second photolithography and etch process is performed after

formation of the trench dielectric layer to create trench openings in the trench dielectriclayer and via openings in the via dielectric layer, where the patterned etch stop layer actsas a hard-mask in forming vias in the via dielectric layer.

申请人：Neng-Kuo Chen,Kuo-Hwa Tzeng,Cheng-Yuan Tsai

地址：Sinshih Township TW,Taipei TW,Chu-Pei TW

国籍：TW,TW,TW

代理机构：Slater & Matsil, L.L.P.

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