Data processor having cache memory

专利名称：Data processor having cache memory发明人：Hotta, Takashi,Kurihara, Toshihiko,Tanaka,

Shigeya,Sawamoto, Hideo,Osumi,Akiyoshi,Saito, Koji,Shimamura, Kotaro

申请号：EP94305771.1申请日：19940803公开号：EP0637800A2公开日：19950208

专利附图：

摘要：A data processor has a main memory (203) which stores data and instructions tobe used by the processor, an instruction processor (201) and two cache memories

(100,101). The first cache memory (101) is a large capacity port direct mapped cachememory, and the second cache memory (100) is a small capacity two port set associativecache memory. The instruction processor (201) controls the transfer of data to/from thecache memories (100,102) on the basis of instruction from the main memory, so that dataneeded frequently is stored in the first cache memory (101) and data needed lessfrequently is stored in the second cache memory (100). With such an arrangement, datastored in the second cache memory (100) can be removed therefrom after it has beenaccessed, and other data stored therein, thereby increasing the probability that dataneeded at any time will be in the first or second cache memories (101,100), withoutstoring useless data on the first cache memory (101).

申请人：HITACHI, LTD.

地址：6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 100 JP

国籍：JP

代理机构：Calderbank, Thomas Roger

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