Method of fabricating bit lines by damascene

专利名称：Method of fabricating bit lines by

damascene

发明人：Jing-Horng Gau申请号：US09/206112申请日：19981204公开号：US06071804A公开日：20000606

摘要：A method of fabricating bit lines by damascene. A substrate having a firstdielectric layer is provided, and a bit line contact is formed within the first dielectric layer.A hard material layer is formed on the first dielectric layer to expose the bit line contact.A second dielectric layer is formed on the hard material layer. An opening and a trenchare formed within the second dielectric layer to expose the bit line contact and the hardmaterial layer. A hard material spacer is formed on the sidewall of the opening and thetrench. A tungsten silicide layer fills the opening and the trench to serve as a bit line onthe bit line contact and an interconnect of the bit line.

申请人：UNITED SEMICONDUCTOR CORP.

代理人：J. C. Patents,Jiawei Huang

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