Phasefrequency detector for dejitter applications

专利名称：Phase/frequency detector for dejitter

applications

发明人：Alexis Shishkoff,Barry L. Stakely申请号：US09441977申请日：19991117公开号：US06351508B1公开日：20020226

专利附图：

摘要：A phase/frequency detector includes two D-Q flip-flops, an OR gate, and anexclusive NOR (XNOR) gate. The phase/frequency detector is used in conjunction with aclock dejitter PLL where the underflow and overflow flags from a FIFO are coupled to the

inputs of the OR gate and the Q outputs of the flip-flops are coupled to the inputs of theXNOR gate. The Qb output of each flip-flop is coupled to the D input of the respectiveflip-flop. The recovered clock signal is coupled to the clock input of the first flip-flop andthe output of the VCXO is coupled to the clock input of the second flip-flop. The SETinput of the first flip-flop is coupled to the overflow flag and the RESET input of the firstflip-flop is coupled to the underflow flag. The SET input of the second flip-flop is coupledto the output of the OR gate and the output of the XNOR gate is passed through thefilter to the input of the VCXO. When the phase is locked, the output of the XNOR has a50% duty cycle which causes the voltage across the filter to remain constant whichmaintains a steady VCXO output frequency. The FIFO will either underflow or overflow ifthe recovered clock and the VCXO run at different speeds. In this case, the flip-flopsgenerate correction pulses that will drive the PLL filter voltage to the point where theVCXO is running at the correct frequency.

申请人：TRANSWITCH CORPORATION

代理人：David P Gordon,David S Jacobson,Thomas A Gallagher

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