专利名称：Fabrication of through-silicon vias on silicon
wafers
发明人：Nagarajan Rajagopalan,Ji Ae Park,Ryan
Yamase,Shamik Patel,Thomas Nowak,Li-QunXia,Bok Hoen Kim,Ran Ding,JimBaldino,Mehul Naik,Sesh Ramaswami
申请号：US12978129申请日：20101223公开号：US08283237B2公开日：20121009
专利附图：
摘要：A through-silicon via fabrication method comprises forming a substrate bybonding the front surface of a silicon plate to a carrier using an adhesive layer
therebetween to expose the back surface of the silicon plate. A silicon nitride passivationlayer is deposited on the exposed back surface of the silicon plate of the substrate. Aplurality of through holes are etched in the silicon plate, the through holes comprisingsidewalls and bottom walls. A metallic conductor is deposited in the through holes toform a plurality of through-silicon vias.
申请人：Nagarajan Rajagopalan,Ji Ae Park,Ryan Yamase,Shamik Patel,ThomasNowak,Li-Qun Xia,Bok Hoen Kim,Ran Ding,Jim Baldino,Mehul Naik,Sesh Ramaswami
地址：Santa Clara CA US,Santa Clara CA US,Santa Clara CA US,Redlands CA
US,Cupertino CA US,Cupertino CA US,San Jose CA US,Sunnyvale CA US,Portland OR US,SanJose CA US,Saratoga CA US
国籍：US,US,US,US,US,US,US,US,US,US,US
代理机构：Janah & Associates, P.C.
代理人：Ashok K. Janah
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