专利名称：Fabrication of through-silicon vias on silicon
wafers
发明人：Nagarajan Rajagopalan,Ji Ae Park,Ryan
Yamase,Shamik Patel,Thomas Nowak,Li-QunXia,Bok Hoen Kim,Ran Ding,JimBaldino,Mehul Naik,Sesh Ramaswami
申请号：US12977060申请日：20101222公开号：US08329575B2公开日：20121211
专利附图：
摘要：A through-silicon via fabrication method includes etching a plurality of throughholes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate andon the sidewalls and bottom wall of the through holes. A metallic conductor is thendeposited in the through holes. In another version, which may be used concurrently withthe oxide liner, a silicon nitride passivation layer is deposited on the exposed back surfaceof the silicon plate of the substrate.
申请人：Nagarajan Rajagopalan,Ji Ae Park,Ryan Yamase,Shamik Patel,ThomasNowak,Li-Qun Xia,Bok Hoen Kim,Ran Ding,Jim Baldino,Mehul Naik,Sesh Ramaswami
地址：Santa Clara CA US,Santa Clara CA US,Santa Clara CA US,Redlands CA
US,Cupertino CA US,Cupertino CA US,San Jose CA US,Sunnyvale CA US,Portland OR US,SanJose CA US,Saratoga CA US
国籍：US,US,US,US,US,US,US,US,US,US,US
代理机构：Janah & Associatees, P.C.
代理人：Ashok K. Janah
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容