专利名称：Branch target address cache with hashed
indices
发明人：Sheldon B. Levenstein,David S. Levitan,Lixin
Zhang
申请号：US12024219申请日：20080201公开号：US07962722B2公开日：20110614
专利附图：
摘要：In at least one embodiment, a processor includes at least one execution unitthat executes instructions and instruction sequencing logic, coupled to the at least one
execution unit, that fetches instructions from a memory system for execution by the atleast one execution unit. The instruction sequencing logic including a branch targetaddress cache (BTAC) including a plurality of entries for storing branch target addresspredictions. The BTAC includes index logic that selects an entry to access utilizing a BTACindex based upon at least a set of higher order bits of an instruction address and a set oflower order bits of the instruction address.
申请人：Sheldon B. Levenstein,David S. Levitan,Lixin Zhang
地址：Austin TX US,Austin TX US,Austin TX US
国籍：US,US,US
代理机构：Dillon & Yudell LLP
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