HS1-565ARH资料

SemiconductorHS-565ARHRadiation Hardened High Speed,Monolithic Digital-to-Analog Converter

DescriptionThe HS-565ARH is a fast, radiation hardened 12-bit current out-put, digital-to-analog converter. The monolithic chip includes aprecision voltage reference, thin-film R-2R ladder,referencecontrol amplifier and twelve high-speed bipolar currentswitches.The Harris Semiconductor Dielectric Isolation processprovideslatch-up free operation while minimizing stray capacitance andleakage currents, to produce an excellent combination of speedand accuracy. Also, ground currents are minimized to produce alow and constant current through the ground terminal, whichreduces error due to code-dependent ground currents.HS-565ARH die are laser trimmed for a maximum integral nonlin-earity error of±0.25 LSB at +25oC. In addition, the low noise bur-ied zener reference is trimmed both for absolute value and mini-mum temperature coefficient.March 1996

Features•Devices QML Qualified in Accordance withMIL-PRF-38535•Detailed Electrical and Screening Requirementsare Contained in SMD# 5962-96755 and Harris’ QMPlan•DAC and Reference on a Single Chip•Pin Compatible with AD-565A and HI-565A•Very High Speed:Settles to 0.50 LSB in 500ns Max•Monotonicity Guaranteed Over Temperature•0.50 LSB Max Nonlinearity Guaranteed OverTemperature•Low Gain Drift (Max., DAC Plus Reference) 50ppm/oC•Total Dose Hardness to 100K RAD•±0.75 LSB Accuracy Guaranteed Over Temperature(±0.125 LSB Typical at +25oC)Functional DiagramREF OUTVCC43+10VIREF0.5mA3.5K3K7-VEE12PWRGND24 . . . 13MSBLSB+DACIO(4X IREFX CODE)2.5K9.95K5KBIP.OFF.85K1010VSPAN9OUT1120VSPANApplications•High Speed A/D Converters•Precision Instrumentation•Signal ReconstructionREFIN-619.95KREF5GND-Ordering InformationPART NUMBER5962R9675501VJC5962R9675501VXCHS1-565ARH (SAMPLE)HS9-565ARH (SAMPLE)TEMPERATURE RANGE-55oC to +125oC-55oC to +125oC+25oC+25oCSCREENING LEVELMIL-PRF-38535 Level VMIL-PRF-38535 Level VSampleSamplePACKAGE24 Lead SBDIP24 Lead Ceramic Flatpack24 Lead SBDIP24 Lead Ceramic FlatpackCAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.Copyright © Harris Corporation 1996

Spec NumberFile Number

1

5187953278.2

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HS-565ARHPinoutsHS1-565ARHMIL-STD-1835 CDIP2-T24(SBDIP)TOP VIEWNC1NC2VCC3REF OUT4REF GND5REF IN6-VEE7BIPOLAR RIN8IDAC OUT924BIT 1 IN (MSB)23BIT 2 IN22BIT 3 IN21BIT 4 IN20BIT 5 IN19BIT 6 IN18BIT 7 IN17BIT 8 IN16BIT 9 IN15BIT 10 IN14BIT 11 IN13BIT 12 IN (LSB)10V SPAN1020V SPAN11PWR GND12H59-565ARHMIL-STD-1835 CDFP4-F24(CERAMIC FLATPACK)TOP VIEWNCNCVCCREF OUTREF GNDREF IN-VEEBIPOLAR RINIDAC OUT10V SPAN20V SPANPWR GND123456789101112242322212019181716151413BIT 1 IN(MSB)BIT 2 INBIT 3 INBIT 4 INBIT 5 INBIT 6 INBIT 7 INBIT 8 INBIT 9 INBIT 10 INBIT 11 INBIT 12 IN(LSB)Spec Number

2

518795

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Specifications HS-565ARHAbsolute Maximum RatingsVCC to Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +18VVEE to Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to -18VVoltage on DAC Output (Pin 9). . . . . . . . . . . . . . . . . . . .-3V to +12VDigital Input (Pins 13 - 24) to Power Ground . . . . . . . . . .-1V to +7VRef In to Reference Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±12VBipolar Offset to Reference Ground . . . . . . . . . . . . . . . . . . . . . . .±12V10V Span R to Reference Ground. . . . . . . . . . . . . . . . . . . . . . . . .±12V20V Span R to Reference Ground. . . . . . . . . . . . . . . . . . . . . . . . .±24VJunction Temperature (TJ) (Max). . . . . . . . . . . . . . . . . . . . .+175oCStorage Temperature Range . . . . . . . . . . . . . . . . .-65oC to +150oCLead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . .+300oCThermal InformationThermal Resistance (Typical)θJA(oC/W)θJC(oC/W)SBDIP Package. . . . . . . . . . . . . . . . . .6017Ceramic Flatpack Package8015Maximum Package Power Dissipation at +125oCSBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.83WCeramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . .0.62WIf Device Power Exceeds Package Dissipation Capability, ProvideHeat Sinking or Derate Linearly at the Following Rate:SBDIP Package16.67mW/oCCeramic Flatpack Package12.5mW/oCCAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.Operating ConditionsOperating Voltage Range (VCC) . . . . . . . . . . . . .+11.4V to +16.5VOperating Voltage Range (VEE). . . . . . . . . . . . . . .-11.4V to -16.5VOperating Temperature Range. . . . . . . . . . . . . . . .-55oC to +125oCDigital Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8VDigital Input High Voltage . . . . . . . . . . . . . . . . . . . . .+2.2V to +5.5VTABLE 1.DC ELECTRICAL PERFORMANCE CHARACTERISTICSGROUP ASUB-GROUP1, 2, 31, 2, 3LIMITSTEMPERATURE-55oC to +125oC-55oC to +125oCMIN--TYP-±0.125MAX12±0.75UNITSBitsLSBPARAMETERSResolutionAccuracySYMBOLCONDITIONSVSSD = VSSA = 0V,VCC = +15V, VEE = -15VILEVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,Error Relative to Full ScaleVSSD = VSSA = 0V, VIN = 5.5VVCC = +15V, VEE = -15VVSSD = VSSA = 0V, VIN = 0VVCC = +15V, VEE = -15VVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,+25oC (MonotonicityGuaranteed Over Temp)VSSD = VSSA = 0V,VCC = +15V, VEE = -15VVSSD = VSSA = 0V,VCC = +15V, VEE = -15VVSSD = VSSA = 0V,VCC = +15V, VEE = -15VVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,Available for external loadsVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,All Bits OnVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,All Bits On or OffDigital Input High CurrentDigital Input Low CurrentDifferential NonlinearityIIHIILDLE1, 2, 31, 2, 31, 2, 3-55oC to +125oC-55oC to +125oC-55oC to +125oC--20-0.01-2.0±0.25+1.0-±0.50µAµALSBPower Supply CurrentsVCCVEEReference OutputVoltageReference OutputCurrentOutput CurrentUnipolarIOUT11, 2, 3-55oC to +125oC-1.6-2.0-2.4mAICCIEERef OutIREF1, 2, 31, 2, 31, 2, 31, 2, 3-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC--14.59.91.59.0-9.5102.511.8-10.1-mAmAVmABipolarIOUT21, 2, 3-55oC to +125oC±0.8±1.0±1.2mASpec Number

3

518795

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Specifications HS-565ARHTABLE 1.DC ELECTRICAL PERFORMANCE CHARACTERISTICS(Continued)GROUP ASUB-GROUP1, 2, 3LIMITSTEMPERATURE-55oC to +125oCMIN-TYP±0.01MAX±0.05UNITS% ofF.S.% ofF.S.PARAMETERSOutput OffsetUnipolarSYMBOLVOSCONDITIONSVSSD = VSSA = 0V,VCC = +15V, VEE = -15VFigure 3, R2 = 50Ω FixedVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,R3 and R4 = 50Ω FixedFigure 4BipolarBPOE1, 2, 3-55oC to +125oC-±0.05±0.15Power Supply GainSensitivityVCCVEETemperatureCoefficientsUnipolar ZeroBipolar ZeroGain (Full Scale)External AdjustmentsGain ErrorBipolar Zero ErrorNOTES:1.All voltages referenced to VSSD = VSSA = 0V2.Unless otherwise specified VCC = +15V and VEE = -15V.3.The Power Supply Gain Sensitivity is tested in reference to a VCC = +15V and VEE = -15V.TABLE 2.AC ELECTRICAL PERFORMANCE CHARACTERISTICSTable 2 Intentionally Left Blank. See AC Specifications in Table 3TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICSLIMITSPARAMETERSOutput CapacitanceOutput ComplianceVoltageProgrammable OutputRangesSYMBOLCOUTCONDITIONSf = 1MHzNOTES1, 2111111Gain Adjustment RangeBipolar ZeroAdjustment RangeReference InputImpedanceOutput ResistanceRREFROUTFigures 3, 4Figure 4VSSD = VSSA = 0V, -15VCC = +15V, VEE = -15VVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,Exclusive of Span Resistors1111TEMPERATURE+25oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oCMIN--1.50-2.50-5-10±0.25±0.1515K1.8KTYP20--------20K2.5KMAX-1052.510510--25K3.2KUNITSpFVVVVVV% ofF.S.% ofF.S.ΩΩAEBPAEBPZEWith Internal ReferenceWith Internal ReferenceWith Internal ReferenceFixed 50Ω Resistor for R2Figures 3Fixed 50Ω Resistor for R3 andR4, Figure 4Fixed 50Ω Resistor for R3 andR4, Figure 41, 2, 31, 2, 31, 2, 31, 2, 31, 2, 31, 2, 3-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC-55oC to +125oC------1510±0.10±0.10±0.0522050±0.25±0.25±0.10ppm/oCppm/oCppm/oC% ofF.S.% ofF.S.% ofF.S.+PSS-PSSNote 3Note 31, 2, 31, 2, 3-55oC to +125oC-55oC to +125oC--3151025ppm ofF.S./%ppm ofF.S./%Spec Number

4

518795

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Specifications HS-565ARHTABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS(Continued)LIMITSPARAMETERSSettling Time (Note 3)SYMBOLTS1CONDITIONSVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,High Z External LoadVSSD = VSSA = 0V,VCC = +15V, VEE = -15V,75Ω External LoadVSSD = VSSA = 0V,VCC = +15V, VEE = -15VVSSD = VSSA = 0V,VCC = +15V, VEE = -15VNOTES1TEMPERATURE-55oC to +125oCMIN-TYP350MAX500UNITSnsTS21-55oC to +125oC-150250nsFull Scale TransitionRise TimeFall TimeNOTES:1.The parameters listed in Table 3 are controlled via design or process and are not tested. These parameters are characterized upon initialdesign release.2.24 lead DIP package only.3.Reference the Settling Time discussion and Figure 3.TABLE 4.POST 100 K RAD ELECTRICAL PERFORMANCEPost 100K RAD Electrical Performance Is Per Table 1 (+25oC Only) Except As Follows:LIMITSPARAMETERDIGITAL INPUTSLow CurrentLow VoltageHigh VoltageUNIPOLARFull Scale ErrorBIPOLAROffset ErrorZero ErrorFull Scale ErrorDifferential NonlinearityAccuracyNOTES:1.This parameter is an applied condition of test.TABLE 5.BI DELTA PARAMETERS (±25oC)PARAMETERICCIEEIOUT1IOUT2VOSAEBPOEBPZEIILIIHDELTA LIMIT±1.18mA±1.45mA±240µA±240µA±0.02%±0.15%±0.10%±0.10%±1.0µA±40nABPOEBPZEBPAEDLEILEFigure 4, R3 and R4 = 50Ω FixedFigure 5, R3 and R4 = 50Ω FixedFigure 5, R3 and R4 = 50Ω FixedMonotonicity GuaranteedError Relative to Full Scale-----±0.25±0.25±0.85±1.0±1.0% of F.S% of F.S.% of F.S.LSBLSBAEFigure 3, R2 = 50Ω Fixed-±0.85% of F.S.IILVILVIHVIN = 0.0V(Note 1)(Note 1)-40-2.5-0.5-µAVVSYMBOLCONDITIONS: +25oC ONLYMINMAXUNITSTRISETFALL11-55oC to +125oC-55oC to +125oC--15303060nsnsSpec Number

5

518795

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Specifications HS-565ARHBurn-In Bias Circuit1NC+15VD1C12NC3VCC4REF OUT5REF GND-15VD2+10VD3C3C26REF IN7-VEE8BIP OFF9OUTBIT 124BIT 223BIT 322BIT 421BIT 520BIT 619BIT 718BIT 817BIT 916F0F1F2F3F4F5F6F7F8F9F10F11+10V-15V+15VRadiation Bias Circuit1NC2NC3VCC4REF OUT5REF GND6REF IN7-VEE8BIP OFF9OUTBIT 124BIT 223BIT 322BIT 421BIT 520BIT 619BIT 718BIT 817BIT 916+5V1010V SPANBIT 10151120V SPANBIT 111412PWR GNDBIT 12131010V SPANBIT 10151120V SPANBIT 111412PWR GNDBIT 1213NOTES:D1 = D2 = D3 = IN4002 or EquivalentF0 to F11:VIH = 5.0V±0.5VVIL = 0.0V±0.5VF0 = 100kHz±10% (50% Duty Cycle)F1 = F0/2F7 = F0/128F2 = F0/4F8 = F0/256F3 = F0/8F9 = F0/512F4 = F0/16F10 = F0/1024F5 = F0/32F11 = F0/2048F6 = F0/64NOTE:Power Supply Levels are±0.5VDefinitions of SpecificationsDigital InputsThe HS-565ARH accepts digital input codes in binary formatand may be user connected for any one of three binarycodes. Straight binary, Two’s Complement (see note below),or Offset Binary, (See Operating Instructions).DIGITALINPUTMSB .LSB000 . . .000100 . . .000111 . . .111011 . . .111STRAIGHTBINARYZero0.50FS+FS - 1LSB0.50FS - 1LSBANALOG OUTPUTOFFSETBINARY-FS (Full Scale)Zero+FS - 1LSBZero - 1LSB(NOTE)TWO’SCOMPLEMENTZero-FSZero - 1LSB+FS - 1LSBideal (1 LSB) voltage change for a one bit change in code. ADifferential Nonlinearity of±1 LSB or less guaranteesmonotonicity; i.e., the output always increases and neverdecreases for an increasing input.Settling TimeSettling time is the time required for the output to settle towithin the specified error band for any input code transition.It is usually specified for a full scale or major carry transition,settling to within 0.50LSB of final value.DriftGain Drift - The change in full scale analog output over thespecified temperature range expressed in parts per million offull scale range peroC (ppm of FSR/oC). Gain error ismeasured with respect to +25oC at high (TH) and low (TL)temperatures. Gain drift is calculated for both high (TH - 25oC)and low ranges (+25oC - TL) by dividing the gain error by therespective change in temperature. The specification is thelarger of the two representing worst case drift.Offset Drift - The change in analog output with all bits OFFover the specified temperature range expressed in parts permillion of full scale range peroC (ppm of FSR/oC). Offset errorismeasured with respect to +25oC at high (TH) and low (TL)temperatures. Offset drift is calculated for both high (TH - 25oC)and low (+25oC - TL) ranges by dividing the offset error by theNOTE:Invert MSB with external inverter to obtain Two’sComplement CodingAccuracyNonlinearity - Nonlinearity of a D/A converter is an impor-tant measure of its accuracy. It describes the deviation froman ideal straight line transfer curve drawn between zero (allbits OFF) and full scale (all bits ON).Differential Nonlinearity - For a D/A converter, it is thedifference between the actual output voltage change and theSpec Number

6

518795

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HS-565ARHrespective change in temperature. The specification given isthe larger of the two, representing worst case drift.Power Supply SensitivityPower Supply Sensitivity is a measure of the change in gainand offset of the D/A converter resulting from a change in -15Vor +15V supplies. It is specified under DC conditions andexpressed as parts per million of full scale range per percent ofchange in power supply (ppm of FSR/%).ComplianceCompliance Voltage is the maximum output voltage rangethat can be tolerated and still maintain its specified accuracy.Compliance Limit implies functional operation only andmakes no claims to accuracy.GlitchA glitch on the output of a D/A converter is a transient spikeresulting from unequal internal ON-OFF switching times.Worst case glitches usually occur at half scale or the majorcarry code transition from 011 . . . 1 to 100 . . . 0 or viceversa. For example, if turn ON is greater than turn OFF for011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0exists, such that, the output momentarily glitches towardzero output. Matched switching times and fast switching willreduce glitches considerably.No Trim OperationThe HS-565ARH will perform as specified without calibrationadjustments. To operate without calibration, substitute 50Ωresistors for the 100Ω trimming potentiometers:In Figure 3replace R2 with 50Ω; also remove the network on pin 8 andconnect 50Ω to ground. For bipolar operation in Figure 4,replace R3 and R4 with 50Ω resistors.With these changes, performance is guaranteed as shownunder Specifications, “External Adjustments”. Typicalunipolar zero will be±0.50LSB plus the op amp offset.The feedback capacitor C must be selected to minimizesettling time.R4100ΩREF OUTVCC43R3100ΩBIP.OFF.81120V SPANHS-565ARH+-10VIREF0.5mA619.95KREFIN5REFGND3.5K3KCODEINPUT7-VEEPWRGND24. . . . .13MSBLSB+-9.95KDACIO(4 x IREFx CODE)2.5K95K5K1010V SPANDACOUTVO-+CApplying the HS-565ARHOP AMP SelectionThe HS-565ARH’s current output may be converted tovoltage using the standard connections shown in Figures 3and 4. The choice of operational amplifier should bereviewed for each application, since a significant trade-offmay be made between speed and accuracy. Remembersettling time for the DAC-amplifier combination is(t)2+(t)2R (SEETABLE 7)FIGURE 4.BIPOLAR VOLTAGE OUTPUTCalibrationCalibration provides the maximum accuracy from aconverter by adjusting its gain and offset errors to zero, Forthe HS-565ARH, these adjustments are similar whether thecurrent output is used, or whether an external op amp isadded to convert this current to a voltage. Refer to Table 7for the voltage output case, along with Figure 3 or 4.Calibration is a two step process for each of the five outputranges shown in Table 7. First adjust the negative full scale(zero for unipolar ranges). This is an offset adjust whichtranslates the output characteristic, i.e. affects each code bythe same amount.DAwhere tD, tA are settling times for the DAC and amplifier.100kΩR2100ΩREF OUTVCC43HS-565ARH+-19.95K3.5K3KCODEINPUT7-VEEPWRGND24. . . . .13MSBLSB10VIREF0.5mA+-9.95KDACIO(4 x IREFx CODE)2.5K9+R (SEETABLE 7)5K5K1010V SPANDACOUTBIP.OFF.81120V SPAN100Ω+15VR150kΩ-15VVO6REFIN5REFGND-CNext adjust positive FS. This is a gain error adjustment,which rotates the output characteristic about the negative FSvalue.For the bipolar ranges, this approach leaves an error at thezero code, whose maximum values is the same as forintegral nonlinearity error. In general, only two values ofoutput may be calibrated exactly; all others must toleratesome error. Choosing the extreme end points (plus andminus full scale) minimizes this distributed error for all othercodes.FIGURE 3.UNIPOLAR VOLTAGE OUTPUTSpec Number

7

518795

元器件交易网www.cecb2b.com

HS-565ARHSettling TimeThis is a challenging measurement, in which the resultdepends on the method chosen, the precision and quality oftest equipment and the operating configuration of the DAC(test conditions). As a result, the different techniques in useby converter manufacturers can lead to consistently differentresults. An engineer should understand the advantage andlimitations of a given test methods before using the specifiedsettling time as a basis for design.The approach used for several years at Harris calls for astrobed comparator to sense final perturbations of the DACoutput waveform. This gives the LSB a reasonablemagnitude (814mV for the HS-565ARH, which provides thecomparator with enough overdrive to establish an accurate±0.50LSB window about the final settled value. Also, therequired test conditions simulate the DACs environment for acommon application - use in a successive approximation A/D converter. Considerable experience has shown this to be areliable and repeatable way to measure settling time.The usual specification is based on a 10V step, producedby simultaneously switching all bits from off-to-on (tON) oron-to-off (tOFF). The slower of the two cases is specified,as measured from 50% of the digital input transition to thefinal entry within a window of 0.50 LSB about the settledvalue. Four measurements characterize a given type ofDAC:(a)tON, to final value +0.50LSB(b)tON, to final value -0.50 LSB(c)tOFF, to final value +0.50LSB(d)OFF, to final value -0.50LSB(Cases (b) and (c) may be eliminated unless the overshootexceeds 0.50LSB). For example, refer to Figures 5A and5Bfor themeasurement of case (d).ProcedureAs shown in Figure 5B, settling time equals tX plus thecomparator delay (tD = 15ns). To measure tX,•Adjust the delay on generator number 2 for a tX of severalmicroseconds. This assures that the DAC output hassettled to its final wave.•Switch on the LSB (+5V)•Adjust the VLSB supply for 50% triggering at COMPARA-TOR OUT. This is indicated by traces of equal brightnesson the oscilloscope display as shown in Figure 5B. NoteDVM reading.•Switch to LSB to Pulse (P)•Readjust the VLSB supply for 50% triggering as before,and note DVM reading. One LSB equals one tenth thedifference in the DVM readings noted above.•Adjust the VLSB supply to reduce the DVM reading by5 LSBs (DVM reads 10X, so this sets the comparatorto sense the final settled value minus 0.50 LSB). Com-parator output disappears.•Reduce generator number 2 delay until comparator outputreappears, and adjust for “equal brightness”.•Measure tX from scope as shown in Figure 5B. Settlingtime equals tX + tD, i.e. tX + 15ns.TABLE 7.OPERATING MODES AND CALIBRATIONCIRCUIT CONNECTIONSMODEUnipolar (See Figure 3)OUTPUTRANGE0 to +10V0 to +5VBipolar (See Figure 4)±10V±5V±2.5VPIN 10TOVOVONCVOVOPIN 11TOPin 10Pin 9VOPin 10Pin 9RESISTOR(R)1.43K1.1K1.69K1.43K1.1KAPPLYINPUT CODEAll 0’sAll 1’sAll 0’sAll 1’sAll 0’sAll 1’sAll 0’sAll 1’sAll 0’sAll 1’sCALIBRATIONADJUSTR1R2R1R2R3R4R3R4R3R4TO SET VO0V+9.99756V0V+4.99878V-10V+9.99512V-5V+4.99756V-2.5V+2.49878VSpec Number

8

518795

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HS-565ARHOUTSYNCPULSEPULSEINGENERATORGENERATORTRIGNO. 1NO. 2OUT20V± 20%BIASHS-565ARH2423.............14138115K9.95K105K9B+-2.5K2mA125NCSTROBE INDCOMPARATOROUTBATURN ONTURN OFFOUTCA+3V50%0V-0.50LSB0V-400mV(TURN OFF)2VCVLSBSUPPLYDDIGITALINPUTDACOUTPUT~100kHzP5VSETTLING TIMEtD = COMPARATOR DELAYtX50%COMP.STROBE“EQUAL BRIGHTNESS”COMP.OUTLSB90DVM10200K0.1µF0.8V4V0VFIGURE 5A.FIGURE 5B.Other ConsiderationsGroundsThe HS-565ARH has two ground terminals, pin 5 (REF GND)and pin 12 (PWR GND). These should not be tied togethernear the package unless that point is also thesystem signalground to which all returns are connected. (If such a pointexists, then separate paths are required to pins 5 and 12).The current through pin 5 is near zero DC (Note); but pin 12carries up to 1.75mA of code - dependent current from bits1, 2, and 3. The general rule is to connect pin 5 directly tothe system “quiet” point, usually called signal or analogground. Connect pin 12 to the local digital or power ground.Then, of course, a single path must connect the analog/signal and digital/power grounds.NOTE:Current cancellation is a two step process within the HS-565ARH in which code dependent variations are eliminated,the resulting DC current is supplied internally. First anauxiliary 9-bit R-2R ladder is driven by the complement of theDACs input code. Together, the main and auxiliaryladdersdraw a continuous 2.25mA from the internal ground node, re-gardless of input code. Part of the DC current issupplied bythe zener voltage reference, and the remainder is sourcedfrom the positive supply via a current mirror which is lasertrimmed for zero current through the externalterminal (pin 5).LayoutConnections to pin 9 (IOUT) on the HS-565ARH are most crit-ical for high speed performance. Output capacitance of theDAC is only 20pF, so a small change of additionalcapacitancemay alter the op amp’s stability and affectsettling time. Con-nections to pin 9 should be short and few. Component leadsshould be short on the side connecting to pin 9 (as for feed-back capacitor C). See the Settling Time section.Bypass CapacitorsPower supply bypass capacitors on the op amp will serve theHS-565ARH also. If no op amp is used, a 0.01µF ceramiccapacitor from each supply terminal to pin 12 is sufficient,since supply current variations are small.Die CharacteristicsTransistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200Die Size . . . . . . . . . . . . . . . . . . . . . . . . .179 mils x 107 milsTie Substrate to . . . . . . . . . . . . . . . . . . . .Reference GroundProcess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bipolar - DISpec Number

9

518795

元器件交易网www.cecb2b.com

HS-565ARHDie CharacteristicsDIE DIMENSIONS:

179 mils x 107 mils x 19 milsMETALLIZATION:Type: Al/Copper

Thickness: 16kű2kÅGLASSIVATION:Type: SiO2

Thickness: 8kű1kÅ

WORST CASE CURRENT DENSITY:2.0 x 105 A/cm2

Metallization Mask LayoutHS-565ARH

VCC3

NC3

NC1

A

(MSB)BIT 1

BIT 2

VREF OUT

VREFGND

BIT 3

BIT 4BIT 5

VREF IN

-VS

BIPOLAR

12

BIT 7

IDACOUT

BIT 8BIT 6

BIT 9

10VSPAN

20VSPAN

POWERGND

BIT 12(LSB)

BIT 11

BIT 10

Spec Number

10

518795