The MSM7661 is an LSI device which converts digitally sampled NTSC or PAL video signals to8-bit digital data based on ITU-RBT601.
The input video signals available are composite video signals and S video signals.
The composite video signals are converted to YUV data via a 2-dimensional Y/C separationcircuit.
The A-to-D converted data is data sampled at pixel clock frequency or double pixel clockfrequency (the built-in decimation filter is used). Input signal synchronization can locksynchronization and color burst at high speed through internal digital processing.
FEATURES (• indicates a new feature compared with MSM7660)
•Input video signals include the following two types of digital data that are A-to-D convertedat pixel frequency or double pixel frequency :NTSC/PAL composite video signalNTSC/PAL S video signal
°8-bit Y/8-bit C (CbCr) output (conforms to ITU-RBT601)YCbCr4 : 2 : 2YCbC4 : 1 : 1
•2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S videosignal input)
NTSC: 3 lines/2 lines
PAL: 2 lines (3 virtual lines)
•Input signal synchronization can lock synchronization and color burst at high speed throughinternal digital processing.°Sampling frequency13.5 MHz (ITU-R601)
12.27 MHz (NTSC Square Pixel)14.31818 MHz (NTSC 4Fsc)14.75 MHz (PAL Square Pixel)•Internal AGC/ACC circuit
Switchable between AGC and MGC (fixed gain)
•Built-in decimation filter located in the input stage allows easy configuration of an externalfilter circuit (located ahead of A/D converter).
•Automatic NTSC/PAL recognition (only for ITU-RBT.601)•Sleep mode
•Multiplex signal recognition (Teletext)
Data during vertical blanking is output in 8 bits in Through mode.°I2C-bus interface
•3.3 V single power supply (each I/O pin is 5 V tolerable)•Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7661GS-BK)
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SYNC(CSYNC_L)CLKX2OCLKSELHSYVSYNC_LVVALIDPLLSELCLKX2CLKXOSYSSELHSYNC_LHVALIDODDVCO_CPSynchronization BlockY[7:0]DecimationLuminance BlockYD[7:0]Filterlum.Prologue Block(AGC + LPF)EpilogueBlock(2Dim. Y/C separate)CD[7:0]DecimationLine MemoryFilter(1kbyte) ¥ 2chr.Chrominance Block(ACC + LPF)MODE[3:0]C[7:0]I2C-bus Control LogicTest Control Logic(Output Formatter)SCLSDARESET_LTETEST1TEST2(SLEEP)BLOCK DIAGRAM¡ SemiconductorMSM76612/40元器件交易网www.cecb2b.com
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PIN CONFIGURATION (TOP VIEW)
LLPOL__2DCC2EIX_OCCDDDKYNOXSXNNILLDDYCKSKYYAADDNLSLYLSSVVDNDVGCHSVCSCHVHVOGV43210987654321096666655555555554CD[0]148C[0]CD[1]247C[1]CD[2]346C[2]CD[3]445C[3]CD[4]544C[4]CD[5]643C[5]CD[6]742C[6]CD[7]841C[7]CVBS[0]940Y[0]CVBS[1]1039Y[1]CVBS[2]1138Y[2]CVBS[3]1237Y[3]CVBS[4]1336Y[4]CVBS[5]1435Y[5]CVBS[6]1534Y[6]CVBS[7]1633Y[7]78901234567890121112222222222333DL]]]L1DDDA]0123LLETPEVNC[[[[_EGSDSEEEETSSETDENDDDDDESKELGVOOOOSLLLTSMMMMERPC64-Pin Plastic QFPMSM7661
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MSM7661
PIN DESCRIPTIONS
Pin1 to 89 to 161718192021 to 24
SymbolCD[0 to 7]CVBS[0 to 7]
VDDGNDSCLSDAMODE[0 to 3]
II/OI
I2C-bus clock pinI2C-bus data pin
Mode input pins. These pins are internally pulled-down.MODE[3]MODE[1:0]
0: composite1: S video00: ITU-R60101: Square Pixel 10: 4Fsc (only for NTSC) 11: none
If ITU-R signals are input when registers are set to automatic NTSC/PAL recognition mode, NTSC/PAL is automatically recognized irrespective of MODE2 setting.
2526272829303132
RESET_LPLLSELCLKSELTEST1SLEEPTEGNDVDD
IIIIII
System reset pin (active at \"L\")Unused.
Fixed to \"H\" externally.Clock select input pin.
\"L\" Æ double-speed 27 MHz, \"H\" Æ ordinary 13.5 MHzInput pin for testing. Normally \"L\". Internally pulled down.Sleep mode setting pin. Normally \"L\". Internally pulled down.Input pin for testing. Normally \"L\". Internally pulled down.
MODE[2]
0: NTSC1: PAL
TypeII
Description
Chrominance signal input pin (valid only for S video input)Set each pin to \"L\" level at composite signal input.Composite signal input pin
Luminance signal is input for S video input.
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MSM7661
Pin33 to 4041 to 48495051525354555657SymbolY[7 to 0]C[7 to 0]VDDGNDODDVVALIDHVALIDVSYNC_LHSYNC_LCLKXOSYSSELTypeOOLuminance signal output pinsDescriptionChrominance signal output pinsOOOOOOOField display output pinOutputs \"H\" for odd field.Vertical valid line timing output pinHorizontal valid pixel timing output pinV sync output pinH sync output pinInternal operation clock output pinDisplay select output pin for NTSC-PAL detect / multiplex signal detect / HLOCK sync detect.Selection by register. (Default : NTSC-PAL detect)NTSC mode : \"L\Multiplex signal detect : \"H\"HLOCK sync detect : \"H\"58596061626364CLKX2OVCO_CPSYNCHSYCLKX2GNDVDDOOI/OOIClock output pinUnused.Open normally.Composite sync output. Unused as input pin.Clamp signal timing output pin for A/D converterClock input pin5/40
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MSM7661
ABSOLUTE MAXIMUM RATINGS
ParameterPower Supply VoltageInput VoltagePower ConsumptionStorage TemperatureSymbolVDDVIPWTSTGCondition————Rating–0.3 to +4.5–0.3 to +5.5800–55 to +150UnitVVmW°CRECOMMENDED OPERATING CONDITIONS
ParameterPower Supply VoltagePower Supply Voltage\"H\" Level Input Voltage\"L\" Level Input VoltageOperating TemperatureSymbolVDDGNDVIHVILTaCondition—————Min.3.0—2.200Typ.3.30——25Max.3.6—VDD0.870UnitVVVV°C6/40
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MSM7661
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70°C, VDD = 3.3 V ±0.3 V)Parameter\"H\" Level Output VoltageSymbolVOH
ConditionIOH = –4 mA (*1)IOH = –6 mA (*2)IOH = –8 mA (*3)IOL = 4 mA (*1)\"L\" Level Output VoltageVOL
IOL = 6 mA (*2)IOL = 8 mA (*3)VI = GND to VDD
Input Leak CurrentOutput Leak CurrentPower Supply Current (operating)Power Supply Current (operating)Power Supply Current (SLEEP)SDA Output VoltageSDA Output CurrentIIIOIDDOIDDO2IDDSSDAVLSDAIO
Rpull-down =50 kW (*4)VI = GND to VDDCLK = 27 MHzVDD = 3.3 VCLK = 13.5 MHzVDD = 3.3 VSLEEP ON——–1020–10———03———1401101——+10250+1018015050.4—mAmAmAmAmAVmA——0.4V0.7 VDD
——VMin.Typ.Max.Unit*1:*2:*3:*4:HSYNC_L, VSYNC_L, SYSSEL
Y[7:0], C[7:0], HSY, HVALID, VVALID, ODD, CLKXOCLKX2O
MODE[3:0], SLEEP, TEST1, TE
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AC Characteristics (Single Speed Mode)
ParameterSymbolConditionITU-R601CLKX2 Cycle TimetCLKX1NTSC 4FscNTSC Square PixelPAL Square PixelCLKX2 DutyInput Data Setup TimeInput Data Hold TimeOutput Data Delay Time 1 (*)Output Data Delay Time 2 (*)Output Clock Delay Time (*) (External)Output Clock Delay Time (*) (Internal)SCL Clock Cycle TimeLow Level CycletD_D1tIS1tIH1tODX1tOD1tCXD1tCD1tC_SCLtL_SCL—CLKSEL : HCLKSEL : HCLKSEL : HCLKSEL : HCLKSEL : HCLKSEL : HRpull_up = 4.7 kWRpull_up = 4.7 kWMSM7661
(Ta = 0 to 70°C, VDD = 3.3 V ±0.3 V)Min.————400309366200100Typ.Max.74.0769.8481.567.8—————————————60——32131919——Unitnsnsnsns%nsnsnsnsnsnsnsns(*output load 15 pF)AC Characteristics (Double Speed Mode)
ParameterSymbolConditionITU-R601CLKX2 Cycle TimetCLKX2
NTSC 4FscNTSC Square PixelPAL Square PixelCLKX2 DutyInput Data Setup TimeInput Data Hold TimeOutput Data Delay Time 1 (*)Output Data Delay Time 2 (*)Output Clock Delay Time (*) (External)Output Clock Delay Time (*) (Internal)SCL Clock Cycle TimeLow Level CycletD_D2tIS2tIH2tODX2tOD2tCXD2tCD2tC_SCLtL_SCL
—CLKSEL : LCLKSEL : LCLKSEL : LCLKSEL : LCLKSEL : LCLKSEL : LRpull_up = 4.7 kWRpull_up = 4.7 kW(Ta = 0 to 70°C, VDD = 3.3 V ±0.3 V)Min.————405159366200100Typ.Max.37.0534.940.7533.9—————————————60——32131919——Unitnsnsnsns%nsnsnsnsnsnsnsns(*output load 15 pF)8/40
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¡ SemiconductorInput and Output Timing
CLKSEL:HtCLKX1CLKSEL:LtCLKX2MSM7661
CLKX2
tCXD1CLKX2O
tCD1CLKXO
tIS1not validCVBSCD
tCD2tIS2not validtCXD2tIH1not validtIH2not validRESET_L
tOD1HSY,
HVALID, VVALID,ODD, SYSSEL,Y,C,
HSYNC_L,VSYNC_L
tODX1tOD2tODX2**When changing the state of RESET_L input in double speed mode, avoid doing it in the periodof setup time and hold time (the shaded portion).
I2C-bus Interface Input/Output Timing
The basic input/output timing of the I2C-bus interface is as follows.
SDASCLSStart ConditionMSB12789ACK1tC_SCL23-89ACKPStop ConditionData Line Stable: Data ValidChange of Data AllowedI2C-bus Basic Input/Output Timing
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MSM7661
BLOCK DESCRIPTION
1.
Prologue Block
The prologue block performs Y/C separation by inputting data.
Data can be input either at ordinary pixel frequency (ITU-R : 13.5 MHz) or at double pixelfrequency (ITU-R: 27 MHz).
When the double pixel frequency is used, data is processed after changing to the ordinary pixelfrequency via a decimeter circuit.
By changing the register setting, the decimeter circuit can be bypassed irrespective of whetherdata is input at ordinary pixel frequency or at double pixel frequency.
The prologue block performs Y/C separation using a 2-dimensional adaptive comb filter whencomposite signals (CVBS) are input.
The following operation modes can be changed via the I2C-bus. The * mark indicates a default.The default is a state that is selected when reset.1)Video input mode selectComposite video input *S video input
2)Video input mode select
Auto NTSC/PAL select* (Only for ITU-R601)Dependent on Operation mode selected
When ITU-R601 is selected, the video input mode is automatically determined by the numberof lines per field.3)Operation mode selectNTSC CCIR601MTSC Square PixelNTSC 4FscPAL CCIR601PAL Square Pixel
4)Decimeter circuit pass/bypass selectDecimeter circuit is passed. *Decimeter circuit is bypassed.5)Y/C separation mode selectAdaptive comb filter is used. *Unadaptive comb filter is used.Trap filter is used.
The adaptive comb filter detects the correlation up to 3 lines between continuous lines. The Y/C is separated by the comb filter according to the way of correlation if theses lines are correlated.The Y/C is separated by the trap filter if these lines are not correlated (only 2 lines in the case ofPAL).
In the unadaptive comb filter, the Y/C is always separated by removing the luminancecomponent based on the average of preceding and following lines (when there is the correlationbetween 3 lines).
13.5 MHz*12.27 MHz14.31818 MHz13.5 MHz14.75 MHz
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MSM7661
If the comb filter is not used, the Y/C is separated by the trap filter.The Y/C separation circuit is bypassed by S video signal input.
In adittion, the functions of this block work only when lines are valid as image information.The processing of CVBS signals is not made during V-blanking.2.
Luminance Block
The luminance block removes synchronous signals from the signals containing luminancecomponents after Y/C separation. The signals are corrected and output as luminance signals.The luminance signal output level gain control functions include three selectable modes such asAGC (Auto Gain Control), MGC (manual Gain Control) + No Clamp, and MGC + PedestalClamp.
In the AGC mode, the luminance level amplification is determined by comparing the depth ofSYNC with the reference value. The default is 40IRE which can be changed by the register. Theinput is a sync chip clamp type.
In the MGC + No Clamp mode, the luminance signal output level is not affected by the input, andthe amplification and black level are controlled by setting the register.
In the MGC + Pedestal Clamp mode, the signal output level is clamped to the pedestal level ofthe input. The signal amplification and black level are controllable from the clamped point bysetting the register.
This block can select the follwing operation modes.
1)Use of prefilter and sharp filterUsed*Not used
These filters are used for enhancing the edges of luminance component signals.2)Selection of aperture bandpass filter coefficientMiddle range*High range3)Coring range selectoff*±4LBS±5LBS±7LBS
4)Aperture weighting factor select0*0.250.751.5
The profile of these signals can be corrected by coring and aperture correction.5)Use of pixel position correction circuitUsed*Not used6)AGC loop filter time constant selectSlow
Factor value 1/1024n
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¡ SemiconductorMediumFastFixed
1/64n*1/n0
MSM7661
7)Parameter for AGC reference level fine adjustment8)Parameter for sync separation level fine adjustment
The black level is controlled. When the default is specified, the depestal position is output as ablack level (=16).
9)Pedestral clamp selectonPedestral clamp is not used.*
Pedestral clamp is used. (AGC will not operate)3.
Chrominance Block
This is a chroma signal processing block.The following modes can be selected.1)Use of color bandpass filterUsed*Not used2)ACC loop filter time constant selectSlowMediumFastFixed3)ACC reference level fine adjustment
4)Parameter for burst level fine adjustment
The threshold level for valid chroma amplitude is selected based on a color burst ratio.0.50.25*0.125off5)Color killer mode selectAuto color killer mode*Forcible color killer
6)Parameter for color subcarrier phase fine adjustment
In this block, chroma signals pass through the chroma bandpass filter to cut an unnecessaryband. To maintain a constant chroma level, UV demodulation is performed on these signalsvia the ACC correction circuit. (This filter can be bypassed.)
If the demodulation result does not reach a specified level, color killer signals are generatedto fix the ACC gain. This functions as an auto color killer control circuit.
The UV demodulation result is output as chrominance signals via a low pass filter.
Factor value 1/1024n1/64n*1/n0
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¡ Semiconductor4.
Synchronization Block
MSM7661
This is a synchronizing signal processing block.
Chip output synchronizing signals and synchronizing signals for internal use are generated bythis block. Various signals are output in this block and the following operation modes can beselected.
1)SYNC threshold level adjustment
2-1) Fine adjustment of HSY signal (start side)2-2) Fine adjustment of HSY signal (stop side)
3)HSY signal enable selectHigh LevelActive*
These signal are used to sync chip and clamp timing to the A/D converter4)Fine adjustment of HSYNC_L signal
5-1) Fine adjustment of HVALID signal (start side)5-2) Fine adjustment of HVALID signal (stop side)6-1) Fine adjustment of VVALID signal (start side)6-2) Fine adjustment of VVALID signal (stop side)
The data signals are transmitted or received at the rising edge of the HVALID signal.7) TV, VTR mode selectTV modeVTR mode*
The TV mode outputs a fixed pixel number per one line and absorbs a jitter that does not appearon the TV receiver normally.
The VTR mode outputs the results of decoding in accordance with the HSYNC signal regardlessof whether a jitter exists or not.
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¡ Semiconductor5.
Epilogue Block
MSM7661
The Epilogue Block outputs UV signals from the chrominance block and Y signals from theluminance block in the format based on the signal obtained by setting of the control register.In this block, the following modes can be selected.1)Display of blue back when synchronization fails.OFFON*
2)Output signal Y/CbCr format selectYCbCr4 : 2 : 2*YCbCr4 : 1 : 1
The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an outputformat described later.
3)Selection of 8-bit chroma signal output formatOffset binary*2's Complement4)Output pin enable selectHigh impedanceOutput enable*
5)Multiplex signal detect level adjustment
The levels are configured to be variable when detecting data, such as multiplex signal, which ispresent for the vertical blanking interval.
If defining 60 as the black level and 200 as the white level, the levels between them are valued as100 IRE, the data detect levels are set to 8 steps on a 57 IRE basis.6)Various modes detectionNTSC/PAL detect mode*Multiplex signal detect mode
HSYNC synchronization detect mode7)Output signal phase control6.
I2C Control Block
This is the serial interface block based on the I2C standard of Phillips Corporation.This block functions only as a Slave-Receiver.
The external control can set the internal registers (MRA, MRB, HSYT, etc.).7.
Test Control Block
This block is used to test this LSI. Normally it is not used.
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MSM7661
Register Description
Registers controlled by I2C bus are shown below.
A register setting value with an \"*\" indicates the default.Enter \"0\" to the undefined register when setting registers.Mode Register A (MRA) MRA[3]Video Input modeMRA[2:0] Video Input mode Mode Register B (MRB) Color killer mode MRB[5]Pixel Sampling RatioMRB[4] Blue Back 0:Fix*1:Auto0:TV mode*1:VTR mode*0:Offset binary1:2's Complement*0:external terminal mode1:register mode*0:composite video input1:S video input*000:NTSC CCIR60113.5 MHz001:NTSC Square Pixel12.27 MHz010:NTSC 4Fsc14.31818 MHz100:PAL CCIR60113.5 MHz101: PAL Square Pixel 14.75 MHz *0:Sub Pixel Alignment is used.1:Sub Pixel Alignment is not used. *0: Auto color killer (Chrominance signal levelbecomes \"0\" when color burst level is belowspecified value.) *1: Forced color killer ON (Chrominance signallevel is forced to be \"0\".)*0:(4:2:2) 1: (4:1:1) 0:OFF (Video signal is demodulated andoutput regardless of synchronizationdetection .) *1: AUTO (Blue Back is output when synchro-nization is not detected.) 15/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 MRB[3]MRB[2] Sync enable, clamping pulse0: *1:Data-pass control *0:1: HSY outputs \"HIGH\" level.HSY outputs active. DECIMETER is used at 2X sampling.No DECIMETER is used. (Note) This register becomes valid at doube-speed clock input(27 MHz).MRB[1:0] Y/C separation mode *00: Adaptive comb filter (Operation mode isselected monitoring the correlation of 3lines.) Nonadaptive comb filter (Operation modeis always fixed.) Comb filter is not used. (Trap filter is used.)Undefined 01:10:11: (Note)Adaptive comb filter: Non-adaptive comb filter: 2/3-line comb filter at NTSCComb filter/trap filter at PAL3-line comb filter at NTSC 2-line cosine comb filter at PAL Horizontal Sync Trimmer (HSYT) HSY begin trimmer (8/pixel)HSY stop trimmer (8/pixel) 0xC: –4 (–32)0xC: –4 (–32) to0xB: +11 (+88)to0xB: +11 (+88) Sync Threshold level adjust (STHR) Sync depth 0x0: –0to*0x37:55 to 0xFF:255 (Note)The sync signal detect threshold level is adjusted.Horizontal Sync Delay (HSDL) HSYNC_L delay trimmer (4/pixel) 0x80: –128 (–512)to0x7F: +127 (508) Horizontal Valid Trimmer (HVALT) HVALID begin trimmer (1/pixel)HVALID stop trimmer (1/pixel) 0x8: –8to0x7: +70x8: –8to0x7: +7 16/40 元器件交易网www.cecb2b.com ¡ Semiconductor Vertical Valid Trimmer (VVALT) VVALID stop trimmer (1/line) 0x8: –8to0x7: +7 Luminance Control (LUMC) Output level limiter *0: OFF 1: ON (Note) The limit range is from 16 to 235 at limiter ON.LUMC[6]Use of Pre-filter 0:Prefilter is not used.*1: Prefilter is used.LUMC[5:4] Aperture bandpass select *00:middle range01:10:11:high rangeLUMC[3:2]Coring range select *00:coring off01:+/–4LSB10:+/–5LSB11: +/–7LSBLUMC[1:0] Aperture filter weighting factor *00:001:0.2510:0.7511: 1.5 AGC/Pedestral Loop filter control (AGCLF) AGC loop filter time constant 00:slow*01:medium10:fast11:fixed AGCLF[5:0]AGC reference level 0x20:–32 to 0x1F: +31 MSM7661 17/40 元器件交易网www.cecb2b.com ¡ Semiconductor Sync separation level (SSEPL) Pedestal clamp on/off *0:1: Pedestal clamp is not used.Pedestal clamp is used.(AGC will not operate.) to 0x3F: +63 MSM7661 SSEPL[6:0]Sync separation level0x40:–64 Chrominance Control (CHRC) Undefined C-Output level limiter 0: *OFF 1: ON (Note) The limit range is from16 to 224 at limiter ON.CHRC[2]CHRC[1:0] Chroma bandpass filterColor kill threshold factor 0:00:*01:10:11: OFF *1: ON 0.5 color burst level0.25 color burst level0.125 color burst level0 (Color killer off) ACC Loop filter control (ACCLF) Undefined ACC loop filter time constant 00:*01:10:11:ACC reference level slowmediumfastfixed to 0x0F: +15 ACCLF[4:0]0x10:–16 Hue control (HUE) Hue control 0x80:–180 degrees to 0x7F: 178.6 degrees 18/40 元器件交易网www.cecb2b.com ¡ Semiconductor Optional Mode Register (OMR) Undefined Multiplex signal detection level(VBID etc.) (57IRE)(63IRE)*(68IRE) • •(97IRE)ActiveHi-Z NTSC/PAL SOUT (Multiplex signal detect)HDET (H-Sync detect)Undefined MSM7661 OMR[2]OMR[1:0] Hi-Z on Sleep for Out-pinSignal Indicate mode *0:1:*00:01:10:11: Output phase control for data Y (OPCY) Undefined Output phase control for data Y*0: 1:2:3: normal forward l clockbackward 2 clocksbackward l clock Output phase control for data C (OPCC) Undefined Output phase control for data C*0: 1:2:3: normal forward l clockbackward 2 clocksbackward l clock 19/40 元器件交易网www.cecb2b.com ¡ Semiconductor FUNCTIONAL DESCRIPTION Input Signal Level Input signal is 8 bits in a straight binary format.The recommended input range is shown below. 255246reserved200Iuminancechrominance+DC60input black levelsync013CVBS[7:0] input range MSM7661 20/40 元器件交易网www.cecb2b.com ¡ SemiconductorOutput format The YCbCr 4:2:2 format and 4:1:1 format are shown below.The output format can be changed by register settings. MSM7661 OUTPUTPIXEL BYTE SEQUENCEY7(MSB)Y7Y7Y7Y7Y7Y7Y6Y6Y6Y6Y6Y6Y6Y5Y5Y5Y5Y5Y5Y5Y4Y4Y4Y4Y4Y4Y4Y3Y3Y3Y3Y3Y3Y3Y2Y2Y2Y2Y2Y2Y2Y1Y1Y1Y1Y1Y1Y1Y0(LSB)Y0Y0Y0Y0Y0Y0C7(MSB)Cb7Cr7Cb7Cr7Cb7Cr7C6Cb6Cr6Cb6Cr6Cb6Cr6C5Cb5Cr5Cb5Cr5Cb5Cr5C4Cb4Cr4Cb4Cr4Cb4Cr4C3Cb3Cr3Cb3Cr3Cb3Cr3C2Cb2Cr2Cb2Cr2Cb2Cr2C1Cb1Cr1Cb1Cr1Cb1Cr1C0(LSB)Cb0Cr0Cb0Cr0Cb0Cr0Y point012345C point024YCbCr 4:2:2 formatOUTPUTPIXEL BYTE SEQUENCEY7(MSB)Y7Y7Y7Y7Y7Y7Y7Y7Y6Y6Y6Y6Y6Y6Y6Y6Y6Y5Y5Y5Y5Y5Y5Y5Y5Y5Y4Y4Y4Y4Y4Y4Y4Y4Y4Y3Y3Y3Y3Y3Y3Y3Y3Y3Y2Y2Y2Y2Y2Y2Y2Y2Y2Y1Y1Y1Y1Y1Y1Y1Y1Y1Y0(LSB)Y0Y0Y0Y0Y0Y0Y0Y0C7(MSB)Cb7Cb5Cb3Cb1Cb7Cb5Cb3Cb1C6Cb6Cb4Cb2Cb0Cb6Cb4Cb2Cb0C5Cr7Cr5Cr3Cr1Cr7Cr5Cr3Cr1C4Cr6Cr4Cr2Cr0Cr6Cr4Cr2Cr0C300000000C200000000C100000000C0(LSB)00000000Y point01234567C point04YCbCr 4:1:1 format 21/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 TIMING DESCRIPTION A/D Converter Support Signal The timing wave form of HSY/HCL signals, which measure the sync chip and clamp timing forthe A/D converter, is as follows. CVBSCOLORBURSTHSYA/D Converter Support Signal Line control signal The line control signal timing is as follows. CLKCLKOHVALIDY[7:0]C[7:0]Y0Cb0Y1Cr0Y2Cb2Y3Cr2Y(n)Cb(n)Y(n+1)Cr(n)Line Control Timing 22/40 元器件交易网www.cecb2b.com ¡ SemiconductorTotal Number of Pixels The total number of pixels vary depending on the mode and frequency used, as shown below(default values when typical signals are input). MSM7661 Video and Sampling ModeVideo ModeSampling Rate13.5 MHzNTSC12.27 MHz (SQ)14.32 MHz (4FSC)—13.5 MHzPAL14.75 MHz (SQ)——TotalPixels858780910864944ActivePixels720640768720768Front-porch162881434HBLK PixelsHsync.Back-porch122112134130142Total13814014214417623/40 元器件交易网www.cecb2b.com ¡ SemiconductorVertical Synchronizing Signal The vertical synchronizing signal timing is as follows. 524CVBSHVALIDHSYNC_LVSYNC_LSYNC(CSYNC_L)VVALIDODD262CVBSHVALIDHSYNC_LVSYNC_LSYNC(CSYNC_L)VVALIDODD2632642652662672682692702712832842855251234567892122MSM7661 Vertical Synchronizing Signal (NTSC 60 Hz) 24/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 621CVBSHVALIDHSYNC_LSYNC(CSYNC_L)VSYNC_LVVALIDODD309CVBSHVALIDHSYNC_LSYNC(CSYNC_L)VSYNC_LVVALIDODD6226236246251234562324310311312313314315316317318336337338Vertical Synchronizing Signal (PAL 50 Hz) 25/40 元器件交易网www.cecb2b.com ¡ Semiconductor Horizontal Synchronizing Signal The horizontal synchronizing signal timing is as follows. MSM7661 Y[7:0]HVALIDHSYNC_L60 pixelsHorizontal Timing 26/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 I2C BUS FORMAT The I2C-bus interface input format is shown below. SSlave AddressSymbolSSlave AddressASubaddressData nPStart conditionSlave address 1000001X, 8th bit is write signal.Acknowledge. Generated by slave Subaddress byteData to write to address designated by subaddress.Stop conditionASubaddressAData 0A......Data nAPDescriptionAs mentioned above, the write operation can be executed from subaddress to subaddresscontinuously. When the write operation is executed at subaddresses discontinuously, theAcknowledge and Stop condition formats are input repeatedly after Data 0. If one of the following matters occurs, the decoder will not return \"A\" (Acknowledge).•The slave address does not match. •A non-existent subaddress is specified. •The write attribute of a register does not match \"X\" (read/write control bit).The input timing is shown below. SDASCLSStart ConditionMSB12789ACK1tC_SCL23-89ACKPStop ConditionData Line Stable: Data ValidChange of Data AllowedI2C-bus Basic Input/Output Timing 27/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 OPERATION MODE SETTING The video mode includes ; 1.Internal terminal mode to be directly set by a dedicated terminal2.Register setting mode to be specified by setting the internal registers These modes can be changed by the mode register MRA [4].The reset state (default) is the external terminal mode. The following registers can be set in the external terminal mode.MRA[3]MRA[2 : 0] input signal modeinput mode *0:1:*000:001:010:100:101: Composite video inputS-video inputNTSC ITU-R601NTSC Square PixelMTSC 4FscPAL ITU-R601PAL Square Pixel 13.5 MHz12.27 MHz14.31818 MHz13.5 MHz14.75 MHz OPERATION CLOCK SETTING The operation clock settings at ITU-R601 are shown below. Input clock27.0 MHz27.0 MHz13.5 MHzInput data27.0 MHz13.5 MHz13.5 MHzCLKSEL Pin\"L\"\"L\"\"H\"Register (MRB2)\"0\" (decimation filter used)\"1\" (Unused)\"1\" (Unused)Clock for A/D converterCLKX2O (27 MHz)CLKXO (13.5 MHz)CLKX2O or CLKXO (13.5 MHz)When the double speed clock is used, data can be input at a double speed or at an ordinary speedby setting the internal register (MRB2) and the clock for the A/D converter. The internal processing after decimation filter is performed at an ordinary speed. 28/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 INTERNAL REGISTERS Register List Register FunctionMode Register A (MRA)Mode Register B (MRB)Horizontal Sync Trimmer (HSYT)Sync Threshold level adjust (STHR)Horizontal Sync Delay (HSDL)Horizontal Valid Trimmer (HVALID)Vertical Valid Trimmer (VVALID)Luminance Control (LUMC)AGC/Pedestal Loop Filter Control (AGCLF)Subaddress0123456789ABCDEFData byteD7MRA7MRB7HSYT7STHR7HSDL7D6MRA6MRB6HSYT6STHR6HSDL6D5MRA5MRB5HSYT5STHR5HSDL5D4MRA4MRB4HSYT4STHR4HSDL4D3MRA3MRB3HSYT3STHR3HSDL3D2MRA2MRB2HSYT2STHR2HSDL2D1MRA1MRB1HSYT1STHR1HSDL1D0MRA0MRB0HSYT0STHR0HSDL0HVALID7HVALID6HVALID5HVALID4HVALID3HVALID2HVALID1HVALID0VVALID7VVALID6VVALID5VVALID4VVALID3VVALID2VVALID1VVALID0LUMC7LUMC6LUMC5LUMC4LUMC3LUMC2LUMC1LUMC0AGCLF7AGCLF6AGCLF5AGCLF4AGCLF3AGCLF2AGCLF1AGCLF0SSEPL7SSEPL6SSEPL5SSEPL4SSEPL3SSEPL2SSEPL1SSEPL0CHRC7HUE7OMR7OPCY7OPCC7CHRC6HUE6OMR6OPCY6OPCC6CHRC5HUE5OMR5OPCY5OPCC5CHRC4HUE4OMR4OPCY4OPCC4CHRC3HUE3OMR3OPCY3OPCC3CHRC2HUE2OMR2OPCY2OPCC2CHRC1HUE1OMR1OPCY1OPCC1CHRC0HUE0OMR0OPCY0OPCC0ACCLF7ACCLF6ACCLF5ACCLF4ACCLF3ACCLF2ACCLF1ACCLF0Sync separation level (SSEPL)Chrominance Control (CHRC)ACC Loop Filter Control (ACCLF)Hue Control (HUE)Optional Mode Register (OMR)Output Phase Control for Data Y (OPCY)Output Phase Control for Data C (OPCC)29/40 元器件交易网www.cecb2b.com ¡ Semiconductor Relationship between Register Setting Value and Adjusted ValueHorizontal Sync Trimmer Position adjustment of sync chip clamp timing signalHSYT [7:4] :Adjusting the starting position D E F 00 1 2 3 4 5 6 7 8 9 A B +8+16+24+32+40+48+56+64+72+80+88 MSM7661 Register Setting Value (Ox)C Adjusted Value (Pixel)–32–24–16–8 HSYT [3:0]:Adjusting the end position DEF00123456789AB+8+16+24+32+40+48+56+64+72+80+88Register Setting Value (Ox)CAdjusted Value (Pixel)–32–24–16–8Horizontal Sync Delay Adjustment of the starting position of horizontal sync signalHSDL [7:0] MSB[7 : 4]80123456LSB[3 : 0]789ABCDEF9ABCDEF00+4+8+12+16+20+24+28+321234567–512–448–384–320–256–192–128–64–508–444–380–316–252–188–124–60–504–440–376–312–248–184–120–56–500–436–372–308–244–180–116–52–496–432–368–304–240–176–112–48–492–428–364–300–236–172–108–44–488–424–360–296–232–168–104–40–484–420–356–292–228–164–100–36–480–416–352–288–224–160–96–476–412–348–284–220–156–92–472–408–344–280–216–152–88–468–404–340–276–212–148–84–464–400–336–272–208–144–80–460–396–332–268–204–140–76–456–392–328–264–200–136–72–452–388–324–260–196–132–68–32–28–24–20–16–12–8–4+64+128+192+256+320+384+448+68+132+196+260+324+388+452+72+136+200+264+328+392+456+76+140+204+268+332+396+460+80+144+208+272+336+400+464+84+148+212+276+340+404+468+88+152+216+280+344+408+472+92+156+220+284+348+412+476+96+160+224+288+352+416+480+36+100+164+228+292+356+420+484+40+104+168+232+296+360+424+488+44+108+172+236+300+364+428+492+48+112+176+240+304+368+432+496+52+116+180+244+308+372+436+500+56+120+184+248+312+376+440+504+60+124+188+252+316+380+444+50830/40 元器件交易网www.cecb2b.com ¡ Semiconductor Horizontal Valid Trimmer Position adjustment of horizontal valid pixel timing signalHVALT [7:4] Register Setting Value (Ox)MSM7661 :Adjusting the starting position 89–7A–6B–5C–4D–3E–2F–1001+12+23+34+45+56+67+7Adjusted Value (Pixel)–8HVALT [3:0] Register Setting Value (Ox):Adjusting the end position 89–7A–6B–5C–4D–3E–2F–1001+12+23+34+45+56+67+7Adjusted Value (Pixel)–8Vertical Valid Trimmer Position adjustment of vertical valid line timing signalVVALT [7:4] Register Setting Value (Ox):Adjusting the starting position 8–89–7A–6B–5C–4D–3E–2F–1001+12+23+34+45+56+67+7Adjusted Value (Line)VVALT [3:0] Register Setting Value (Ox):Adjusting the end position 8–89–7A–6B–5C–4D–3E–2F–1001+12+23+34+45+56+67+7Adjusted Value (Line)AGC Loop filter controlAGCLF [5:0] Register SettingValue(Ox):Adjusting sync level MSB [5 : 4]3–16–15–14–13–12–11–10–9–8–7–6–5–4–3–2–100+1+2+3+4+5+6+7+8+9+10+11+12+13+14+151+16+17+18+19+20+21+22+23+24+25+26+27+28+29+30+312–32–31–30–29–28–27–26–25–24–23–22–21–20–19–18–170123456LSB[3 : 0]789ABCDEF31/40 元器件交易网www.cecb2b.com ¡ SemiconductorSync separation levelSSEPL [6:0] :Adjusting the blanking level Register SettingValueMSB [6 : 4](Ox)456701230–64–48–32–160+16+32+481–63–47–31–15+1+17+33+492–62–46–30–14+2+18+34+503–61–45–29–13+3+19+35+514–60–44–28–12+4+20+36+525–59–43–27–11+5+21+37+536–58–42–26–10+6+22+38+54LSB7–57–41–25–9+7+23+39+55[3 : 0]8–56–40–24–8+8+24+40+569–55–39–23–7+9+25+41+57A–54–38–22–6+10+26+42+58B–53–37–21–5+11+27+43+59C–52–36–20–4+12+28+44+60D–51–35–19–3+13+29+45+61E–50–34–18–2+14+30+46+62F–49–33–17–1+15+31+47+63ACC Loop filter controlACCLF [4:0] :Adjusting the color burst level Register SettingValueMSB [4](Ox)100–1601–15+12–14+23–13+34–12+45–11+56–10+6LSB7–9+7[3 : 0]8–8+89–7+9A–6+10B–5+11C–4+12D–3+13E–2+14F–1+15MSM7661 32/40 元器件交易网www.cecb2b.com ¡ Semiconductor Hue control Adjustment of color subcarrier phaseHUE [7:0] Register SettingValue(Ox)MSM7661 MSB [7 : 4]89ABC–90.0–88.6–87.2–85.8–84.4–83.0–81.6–80.2–78.8–77.3–75.9–74.5–73.1–71.7–70.3–68.9D–67.5–66.1–64.7–63.3–61.9–60.5–59.1–57.7–56.3–54.8–53.4–52.0–50.6–49.2–47.8–46.4E–45.0–43.6–42.2–40.8–39.4–38.0–36.6–35.2–33.8–32.3–30.9–29.5–28.1–26.7–25.3–23.9F–22.5–21.1–19.7–18.3–16.9–15.5–14.1–12.7–11.3–9.8–8.4–7.0–5.6–4.2–2.8–1.40+0.0+1.4+2.8+4.2+5.6+7.0+8.4+9.8+11.3+12.7+14.1+15.5+16.9+18.3+19.7+21.11+22.5+23.9+25.3+26.7+28.1+29.5+30.9+32.3+33.8+35.2+36.6+38.0+39.4+40.8+42.2+43.62+45.0+46.4+47.8+49.2+50.6+52.0+53.4+54.8+56.3+57.7+59.1+60.5+61.9+63.3+64.7+66.13+67.5+68.9+70.3+71.7+73.1+74.5+75.9+77.3+78.8+80.2+81.6+83.0+84.4+85.8+87.2+88.64+90.0+91.4+92.8+94.2+95.6+97.0+98.4+99.85670123456LSB[3 : 0]789ABCDEF–180.0–157.5–135.0–112.5–178.6–156.1–133.6–111.1–177.2–154.7–132.2–109.7–175.8–153.3–130.8–108.3–174.4–151.9–129.4–106.9–173.0–150.5–128.0–105.5–171.6–149.1–126.6–104.1–170.2–147.7–125.2–102.7–168.8–146.3–123.8–101.3–167.3–144.8–122.3–165.9–143.4–120.9–164.5–142.0–119.5–163.1–140.6–118.1–161.7.–139.2–116.7–160.3–137.8–115.3–158.9–136.4–113.9–99.8–98.4–97.0–95.6–94.2–92.8–91.4+112.5+135.0+157.5+113.9+136.4+158.9+115.3+137.8+160.3+116.7+139.2+161.7+118.1+140.6+163.1+119.5+142.0+164.5+120.9+143.4+165.9+122.3+144.8+167.3+101.3+123.8+146.3+168.8+102.7+125.2+147.7+170.2+104.1+126.6+149.1+171.6+105.5+128.0+150.5+173.0+106.9+129.4+151.9+174.4+108.3+130.8+153.3+175.8+109.7+132.2+154.7+177.2+111.1+133.6+156.1+178.633/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 Filter Characteristics Band Pass Filter (NTSC ITU-R601)0–20]B–40d[ leveL–60–80–1000123456Frequency [MHz]Band Pass Filter (PAL ITU-R601)0–20]B–40d[ leveL–60–80–1000123456Frequency [MHz]34/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 Trap Filter (NTSC ITU-R601)0–20]B–40d[ leveL–60–80–1000123456Frequency [MHz]Trap Filter (PAL ITU-R601)0–20]B–40d[ leveL–60–80–1000123456Frequency [MHz]35/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 Pre Filter0–20]B–40d[ leveL–60–80–1000123456Frequency [MHz]Sharp Filter0–20]B–40d[ leveL–60–80–1000123456Frequency [MHz]36/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 Decimation Filter0–20]B–40d[ leveL–60–80–100024681012Frequency [MHz]*The characteristics of the various filters shown above are based on design data. 37/40 元器件交易网www.cecb2b.com ¡ Semiconductor BASIC APPLICATION CIRCUIT EXAMPLEApplication 1 Mode setting Video signal: NTSC-compositeCLKX2: 27 MHz3.3 VMSM7661 I2CControllerTEST2(SLEEP)HSYSDALPF1Input circuitA/D C8CVBS0CVBS7CD0CD7C0...C7Y0...Y78RESET_LSCLVDDVideo in88Framememoryorimage LSIMSM7661VSYNC_LHSYNC_LSYSSELCLKSELPLLSELMODE0MODE1MODE2MODE3CLKXO2SYNCVC0_CPCLKX2HVALIDVVALIDODDCLKXOOSCGNDLLLLDip SWA/D C: CXD1179Q (SONY)LPF1: 628LJN-1471 (TOKO)3.3 V38/40 元器件交易网www.cecb2b.com ¡ SemiconductorApplication 2 Mode setting Video signal: NTSC-compositeCLKX2: 13.5 MHz3.3 VMSM7661 I2CControllerTEST2(SLEEP)HSYSDALPF1Input circuitA/D C8CVBS0CVBS7CD0CD7C0...C7Y0...Y78RESET_LSCLVDDVideo in88Framememoryorimage LSIMSM7661VSYNC_LHSYNC_LSYSSELCLKSELPLLSELMODE0MODE1MODE2MODE3CLKXO2SYNCVC0_CPCLKX2HVALIDVVALIDODDCLKXOOSCGNDLLLLDip SWA/D C: upc659 (NEC)LPF1: 628LJN-1471 (TOKO)3.3 V39/40 元器件交易网www.cecb2b.com ¡ Semiconductor MSM7661 PACKAGE OUTLINES AND DIMENSIONS (Unit : mm) 64-Pin Plastic QFP 40/40 因篇幅问题不能全部显示，请点此查看更多更全内容