¡ Semiconductor
MSM6636
SAE-J1850 Communication Protocol Conformity Transmission Controller for Automo-tive LAN
GENERAL DESCRIPTION
The MSM6636 is a transmission controller for automotive LAN based on data communicationprotocol SAE-J1850. This LSI can realize a data bus topology bus LAN system with a PWM bitencoding method (41.6 K bps). In addition to a protocol control circuit, MSM6636 has an enclosedquartz oscillation circuit, host CPU interface (clock synchronous serial / UART), a transmit/receive buffer, and a bus receiver circuit that decreases the burden on the host CPU.
FEATURES
•Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issuedAugust 12, 1991)
•CSMA/CD (Carrier-sense multiple access with collision detection)•Internal transmit buffer (1 frame) and receive buffer (2 frames)•Bit encoding: PWM (Pulse Width Modulation)•Transmission Speed: 41.6K bps
•Multi-address setting with physical addressing: 1 type / functional addressing: 15 types•Address filter function by multi-addressing (broadcasting possible)•Automatic retransmission function by arbitration loss and non ACK•3 types of in-frame response support:
qSingle-byte response from a single recipient
wMulti-byte response from a single recipient (with CRC code)
eSingle-byte response from multiple recipients (ID response as ACK)•Error detection by cyclic redundancy check (CRC)•Various communication error detections
•Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function•Host CPU interface is LSB first / serial, 4 modes supportedqClock synchronous serial (no parity)Normal mode:8-bit dataMPC Mode:8-bit data + MPC bit (1: address / 0: data select bit)wUART (yes/no parity selectable)
Normal mode:1 start bit + 8-bit data + (parity) + 1 stop bitMPC mode:1 start bit + 8-bit data + MPC bit + (parity) + 1 stop bit•Sleep Function
Low current consumption mode by oscillation stop (IDS Max < 50µA)SLEEP / WAKE UP control from host CPU, WAKE UP via LAN bus•Available package 18pin DIP, 18 pin QFJ (PLCC) and 24pin SOP.
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MSM6636¡ Semiconductor
BLOCK DIAGRAM
Buffer RegisterReceiveRegisterSerial InterfaceReceiveBufferS-PConverterCRCCheckerLAN ControllerPWMDecoderDegitalFilterBusReceiverLANBusInputAddress RegisterCPUAddressFilterReceive ControllerStatus RegisterTransmission RegisterCRCGeneratorP-SConverterTransmission ControllerResponse Registerx'talClockGeneratorPWMEncoderLANBusOutputMSM66362
¡ SemiconductorMSM6636
PIN CONFIGURATION (TOP VIEW)
18pin Plastic DIP AVDD1BO–BI–BI+BO+
2345
181716151413121110
18pin Plastic QFJ BO–AVDDDVDDRESAVDDBO–BI–BI+BO+NCNCNCAGNDU-CM-NDGND
12345678910111224pin Plastic SOP
242322212019181716151413DVDDRESINTTXDRXDSCLK/PAEA-DOSC0
BI– BI+BO+AGNDU-C
345672118171615141312INTTXDRXDSCLK/PAEA-D
AGND6U-CM-N
78
M-NDGNDOSC1OSC0DGND9OSC1
891011DVDDRESINTTXDRXDNCNCNC
SCLK/PAEA-DOSC0OSC1
NC: No Connection
PIN DESCRIPTION
Pin #
Pin NameAVDDBO –BI –BI +BO +AGNDU - CM - NDGNDOSC 1OSC 0A - DSCLK / PAERXDTXDINTRESDVDD
DIP/QFJ123456789101112131415161718
SOP123459101112131415162021222324
I/O—OIIO—II—OIIIIOOI—
Function
Analog power supply pinLAN - BUS output –LAN - BUS input –LAN - BUS input +LAN - BUS output +Analog ground pin0: UART
1: clock synchronous serial select pin
1:normal mode select pin
0: MPC modeDigital ground pinCrystal oscillation outputCrystal oscillation input0: data communication1: address communicationSerial clock input/Parity select pinSerial data input pinSerial data output pinInterrupt output pinReset input pinDigital power supply pin
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MSM6636¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS
DGND = AGND = 0V
ParameterPower Supply Voltage
Input VoltageOutput VoltagePower DissipationStorage Temperature
SymbolDVDD, AVDD
VIVOPD(DIP)*1PD(QFJ)*2PD(SOP)*3TSTG
AVDD = DVDDAVDD = DVDDTa = 25°CTa = 25°CTa = 25°CCondition
Rated Value-0.3~7.0-0.3~DVDD+0.3-0.3~DVDD+0.3
860960830-55~150
UnitVVVmWmWmW°C
PD(DIP)*1:18PIN DIP package power dissipationPD(QFJ)*2:18PIN QFJ package power dissipationPD(SOP)*3:24PIN SOP package power dissipationPower Dissipation Curve
< 18PIN DIP package >
1000860500
Power dissipation PD(QFJ) [mW]Power dissipation PD(DIP) [mW]1000960
< 18PIN QFJ package >
500
-4025125150-4025125150
Ambient temperature Ta (°C)< 24PIN SOP package >
Ambient temperature Ta (°C)
Power dissipation PD(SOP) [mW]1000830500
-4025125150
Ambient temperature Ta (°C)
4
¡ SemiconductorMSM6636
OPERATION RANGE
DGND = AGND = 0V
ParameterSymbolConditionRated ValueUnitPower Supply VoltageDVDD, AVDD
AVDD = DVDD4.5~5.5VOperating FrequencyfOSCDVDD = AVDD = 5V±10%
2~16MHzOperating Temperature
Ta
-40~+125
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD = AVDD = 5V±10%, DGND = AGND = 0V, Ta = -40 ~ +125°C
ParameterSymbolConditionApplicationMINTYP MAXUnitH Level Input Voltage VIH1—ADVDD ¥ 0.8 —DVDD + 0.3VL Level Input Voltage VIL1—ADGND - 0.3—DVDD ¥ 0.2VH Level Input Voltage VIH2—FDVDD - 2.0—DVDD + 1.0VL Level Input Voltage VIL2—FDGND - 1.0
—DGND + 2.0
VReceiver Hysteresis Width VH—F100—400mVH Level Input CurrentIIH1VI = VDDB——+1µAL Level Input CurrentIIL1VI = 0VB——- 1µAH Level Input CurrentIIH2VI = VDDC——+1µAL Level Input CurrentIIL2VI = 0VC——- 100µAH Level Input CurrentIIH3VI = VDDBI (+)——+ 100µAL Level Input CurrentIIL3VI = 0VBI (-)——- 100µAH Level Output Voltage VOH1IO = -400µADDVDD - 0.4
——VL Level Output Voltage VOL1IO = +3.2mAD——DGND + 0.4
VH Level Output Voltage VOH2IO = -4.0mAEDVDD - 0.4
——VL Level Output Voltage VOL2IO = +4.0mA
E——DGND + 0.4
VGND Offset VoltageVOFF————±1VCurrent Consumption 1IDSDuring sleep———50µACurrent Consumption 2
If = 16MHz,DD
no load
—
—
—
10
mA
A: RES, SCLK/PAE, RXD, U-C, M-N, A-D, OSC0B: SCLK/PAE, RXD, U-C, M-N, A-DC: RESD: TXD, INTE: BO-, BO+F: BI-, BI+
5
MSM6636AC ChacteristicsPWM Bit Timing
Transmit
min23.646.9014.8730.5447.2838.4247.2870.9294.568.86
typ24.007.0015.0031.0048.0039.0048.0072.0096.009.00
max24.367.1115.2331.4748.7239.5948.72——9.14
¡ Semiconductor
ParameterBit Length\"1\" Dominant Width\"0\" Dominant Width\"SOF\" Dominant Width\"SOF,BRK\" Length\"BRK\" Dominant Width\"EOD\" + Bit Length\"EOF\" + Bit Length\"EOF + IFS\" + Bit Length\"0\" Passive Width
SymbolTP1TP2TP3TP4TP5TP6TP7TP8TP9TP10
Receivemin21.005.0013.0029.0045.0037.0043.0069.0086.004.00
max28.0012.0020.0036.0052.0044.0051.0076.00—15.00
Unitµsµsµsµsµsµsµsµsµsµs
Note:DVDD = AVDD = 5 V ± 10%, Ta = -40 ~ +125˚C, In setting 41.6 K bps
Dominant
\" 1 \"
PassiveDominant
\" 0 \"
Passive
TP3TP1TP10TP2Dominant
\" SOF \"
Passive
TP4TP5Dominant
\" EOD \"
Passive
LAST BITTP7\" EOF \"\" IFS \"
DominantPassive
LAST BITTP8TP9 Dominant
\" BRK \"
Passive
TP6TP5EOFIFSEOD6
¡ SemiconductorMSM6636
CPU Serial Interface TimingmClock synchronous Serial
DVDD=AVDD=5V±10%, Ta =-40~+125°C
Parameter
OSCO (source oscillation) Pulse CycleSCLK-L Interval WidthSCLK-H Interval WidthSCLK ≠ - RXD Setup TimeSCLK ≠ - RXD Hold TimeSCLK ≠ - TXD Output Delay TimeA-D - SCLK ≠ Setup TimeSCLK ≠ - A-D Hold TimeSCLK Frame Interval Time *1SCLK Frame Interval Time *2
SymboltøtCKLWtCKHWtSRStSRHtSTDtAStAHtINT1tINT2
Min628tø8tø4tø4tø4tø08tø8tø16tø
Typ——————————
Max500————6tø + 100————
Unitnsnsnsnsnsnsnsnsnsns
SCLK Frame Interval Time *1
Between “Communication type (WR) and address setting” frame and “WR data” frame.Between “WR data” frame and “WR data” frame during continuous WR.
SCLK Frame Interval Time *2
Between “Communication type (RD) and address setting” frame and “RD data” frame.Between “RD data” frame and “RD data” frame during continuous RD.
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MSM6636¡ Semiconductor
mUART
DVDD=AVDD=5V±10%, Ta =-40~+125°C
Parameter
A-D - STOP bit ≠ Setup TimeSTOP bit Ø – A-D Hold TimeSTART bit Ø – TXD Output Delay TimeWrite Frame Interval Time *3Read Frame Interval Time *4
SymboltUAStUAHtUTDtINT3tINT4
Min0048tø010tø
Typ—————
Max——50tø + 100
——
Unitnsnsnsnsns
Write Frame Interval Time *3
Between “Communication type (WR) and address setting” frame and “WR data” frame.Between “WR data” frame and “WR data” frame during continuous WR.Read Frame Interval Time *4
Between “Communication type (RD) and address setting” frame and “RD data” frame.
8
¡ SemiconductorMSM6636
Wakeup Input Signal
DVDD=AVDD=5V±10%, Ta =-40~+125°C
Parameter
LAN bus Passive Æ Dominant Change Pulse WidthRXD Terminal Input Pulse WidthBus Receiver Stable Time *5
SymboltWDtWRtRS
Min73001
Typ———
Max———
Unitµsnsµs
tøOSC0
tUASA-DRXD
STOPtINT3tINT4STARTtUAHTXD
tUTDSTARTSTOP bit TerminationNote: The time chart shows the wakeup input signals from each sleep statusBus Receiver Stable Time *5
The stable time of the bus receiver is from just after wakeup to the restart of message trans-mission and reception. However, the clock oscillation source should use an external clock.(A clock is input even in the sleep status.)
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MSM6636¡ Semiconductor
Fault Tolerant Function Operation Conditions
DVDD=AVDD=5V±10%, Ta =-40~+125°C, In setting 41.6Kbps
Parameter
LAN bus (+) VDD Short Circuit Detection Pulse WidthLAN bus (-) GND Short Circuit Detection Pulse WidthLAN bus (-) VDD Short Circuit Detection Pulse Width
SymboltPVtNGtNV
Min548485
Typ————
Max————
Unitµsµsµsµs
LAN bus (+) GND Short Circuit Detection Pulse WidthtPG
BUS(+)BUS(-)
tPGBUS(+)BUS(-)
tNVtNGtPVReset Input Pulse Width
DVDD=AVDD=5V±10%, Ta=–40~+125°C
Parameter
Reset Input Pulse Width
SymboltRES
Min0.1
Typ—
Max—
Unitµs
RES
tRES10
¡ SemiconductorMSM6636
APPLICATION EXAMPLE
Host CPU and LAN bus Connection Example
Host CPU and LAN bus connection example of MSM6636 is shown below.
Unit AHost CPUSOUTSININTCLKOUTOPENMSM6636DVDDAVDDRXDTXDBO (+)INTOSC0BI (+)OSC1SCLK / PAEBI (-)U - CM - NBO (-)A - DRESDGNDAGNDZDZDRESUnit B...Bus +Bus -The above connection example is when \"UART, MPC and parity no mode\" was used as the\"host CPU interface, and when CLKOUT output of the host CPU\" was used as the clock forMSM6636.
Depending on the control target, an optimum host CPU (number of ports, A/D converter yes/ no) can be selected, and an optimum system can be constructed.
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