专利内容由知识产权出版社提供
专利名称：Process for fabricating a semiconductor
integrated circuit device having the multi-layered fin structure
发明人：Hirohisa Usuami,Kazuyuki
Tsunokuni,Masayuki Kojima,Kazuo Nojiri,KeijiOkamoto
申请号：US08/411149申请日：19950327公开号：US05661061A公开日：19970826
摘要：A process for forming an upper-layer fin and a lower-layer fin of a storageelectrode, and a semiconductor integrated circuit device fabricated by the process. Whentwo-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower- layer fin by the dry-etching method using a first mask, the upperpolycrystalline silicon film is patterned at first so far as to form the clearance of theupper-layer fins with the minimum working size of the memory cells of a DRAM, to formthe upper-layer fin. Next, the lower- layer fin is formed by the dry-etching method usinga second mask which has a pattern enlarged in self-alignment from the pattern of thefirst mask, so that it is given a larger horizontal size than that of the upper- layer fin.
申请人：HITACHI, LTD.,HITACHI ULSI ENGINEERING CORPORATION
代理机构：Antonelli, Terry, Stout & Kraus, LLP
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