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专利名称：Wafer level chip-scale package发明人：Jen-Kuang Fang申请号：US10382029申请日：20030304公开号：US06713870B2公开日：20040330
专利附图：
摘要：A wafer level chip-scale package comprises a chip including a plurality of metalpads individually formed on each of the bonding pads. In the same metal circuit layerwhere metal pads exist, bump pads are arranged in a matrix configuration, whereinalmost all of them are electrically connected one by one to bonding pads through
connection traces. Bump pad isolated by lacking connection trace has an extensionportion of itself, and the resilient passivation layer does not overlay the bump pad andextension portion. There is a metal wire used to connect the extension portion of thebump pad with the corresponding metal pad, which is also not overlaid by the resilientpassivation layer. Therefore, the metal wire can directly cross over other connectiontraces to achieve the electrical connection on a shorter route.
申请人：ADVANCED SEMICONDUCTOR ENGINEERING, INC.
代理人：Seyfarth Shaw LLP
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