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专利名称：Wafer level chip scale package and method
of manufacturing the same
发明人：Yu-Hsiang Hu,Wei-Yu Chen,Hung-Jui
Kuo,Wei-Hung Lin,Ming-Da Cheng,Chung-ShiLiu
申请号：US14192374申请日：20140227公开号：US09837278B2公开日：20171205
专利附图：
摘要：A semiconductor structure includes a die including a top surface and a sidewall,
and a molding surrounding the die and including a top surface, a sidewall interfacing withthe sidewall of the die, and a curved surface including a curvature greater than zero andcoupling the sidewall of the molding with the top surface of the molding.
申请人：TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
地址：Hsinchu TW
国籍：TW
代理机构：WPAT, P.C.
代理人：Anthony King,Kay Yang
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