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专利名称：Data interface and high-speed
communication system using the same
发明人：Shigeki Yamakawa,Hiroshi Gokan,Akio
Ohtsuji
申请号：US09331773申请日：19990624公开号：US06357015B1公开日：20020312
专利附图：
摘要：A data interface for communicating data between processors having: a writing-side register group in which data in a writing-side processor which transmits data is
written in response to a clock signal; a reading-side register group into which the datawritten into the writing-side register group is transferred and written in response to alater clock operation, the data being read out by a reading-side processor of a datareceiving side; a write controller for selectively writing data in a register in the writing-side register group in accordance with an address signal and a write signal of the writing-side processor; and a read controller for selectively reading data from a register in thereading-side register group in accordance with an address signal of the reading-sideprocessor; so that a double buffer structure consisting of the writing-side buffers and thereading-side buffers causes the address signal and the data signal to individually beconnected in the writing side and the reading side. Thus, the respective processors areable to transfer data without mutual interference.
申请人：MITSUBISHI DENKI KABUSHIKI KAISHA
代理机构：Leydig, Voit & Mayer, Ltd.
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